Multiple Cell Upsets Research Articles

Neutron-Induced Multiple-Cell Upsets in 20-nm Bulk SRAM: Angular Sensitivity and Impact of Multiwell Potential Perturbation

Neutron-induced multiple-cell upsets (MCUs) are studied in a 20-nm bulk SRAM by irradiation experiments using atmospheric-like neutrons at several angles of incidence. The evaluation of soft error rates reveals that the multiple-bit upset rate significantly increases at grazing incidence, indicating the possibility that the efficiency of error-correction codes is reduced depending on the device orientation in the terrestrial environment. The analyses of the characteristics of the MCU events confirm that the forward emission of secondary ions, the geometry of SRAM cells, and the parasitic bipolar effects are the key factors in determining the angular sensitivity of MCUs. Our analysis unveils the unique data pattern dependence in the occurrence probability of gap structures in fail bit patterns. Based on the consideration of potential perturbations in multiple p-wells, multi-well coupled potential unbalancing is found to be the plausible mechanism underlying this observation. The detailed analyses of fail bit maps with internal node voltages demonstrate that observed gap structures are consistent with the configuration induced by this mechanism.

Total Ionizing Dose Influence on the Single-Event Multiple-Cell Upsets in 65-nm 6-T SRAM

We investigated the total ionizing dose (TID) influence on the single-event multiple-cell upsets (MCUs) in 65-nm 6-T static random-access memory and found that MCU sensitivity of the device is enhanced by TID. MCU caused by particle strike in pMOSFET (p-hits) or nMOSFET (n-hits) is distinguished by the MCU pattern. Analysis of MCU pattern shows that both p-hits MCU and n-hits MCU are enhanced by TID, and they have different mechanisms. Enhancement of n-hits MCU is due to the positive threshold voltage shift ( $\Delta V$ th) of the pull-up pMOSFET, while p-hits MCU is strengthened by the increase in the equivalent resistance of p-well contacts caused by oxide-trapped charges (Not) trapped in the shallow trench isolation.

Low Delay 3-Bit Burst Error Correction Codes

The increasing importance of Multiple Cell Upsets (MCUs) in modern memories has spurred research on error correction codes that can correct adjacent bit errors. For example, Double Adjacent Error Correction (DAEC), 3-bit burst and 4-bit burst codes have been proposed in the last years. However, as the error correction capabilities are increased so is the complexity of the encoder and decoder circuits. This directly impacts the encoding and decoding delay and thus limits the use of the codes in high speed memories. To reduce the complexity, some techniques have been proposed recently. Those include more advanced optimization programs to find codes with a lower number of ones in the parity check matrix or the interleaving of data and parity check bits to simplify the decoding. In this paper, those techniques are combined to design more efficient 3-bit burst error correction codes. The encoders and decoders for the proposed codes have been implemented and compared with the state of the art 3-bit burst error correction codes. The results show that the new codes reduce the encoder and decoder delay significantly. Therefore, the proposed codes provide memory designers with a more efficient option to implement protection against 3-bit burst errors for high speed memories.

Characterizing SRAM and FF soft error rates with measurement and simulation

Soft error originating from cosmic ray is a serious concern for reliability demanding applications, such as autonomous driving, supercomputer, and public transportation system. Also, as the number of electronic devices increases, consumer electronics may require higher reliability than ever. On the other hand, device miniaturization and lower voltage operation degrade the immunity of SRAM and flip-flops in VLSI, and then soft error countermeasures will be demanded in more and more products. This paper characterizes and discusses soft error rates of SRAM and flip-flops in the terrestrial environment. Measured soft error rates of bulk and FDSOI SRAMs are presented. Also, the multiplicity and mechanism of multiple cell upsets (MCUs), which can spoil error correction code (ECC), are discussed. Flip-flops are also sensitive to radiation, but its protection is not well established since ECC cannot be applied. This paper reviews redundant FFs that are developed aiming at higher radiation immunity and demonstrates the resilience improvement with irradiation test results. Also, the importance of layout design is pointed out with a comparative study. Simulation, on the other hand, is a key technology to understand the soft error mechanism and guide radiation aware design for higher reliability. This paper outlines a physics-based multi-scale Monte Carlo simulation framework tailored for soft error simulation. The simulation flow and the model construction are explained, and some important implications are derived from the simulation results that assume 65-nm to 25-nm SRAMs. Finally, this article touches on future trends regarding device structure and overlooked secondary cosmic rays. The advantage and unique features of FinFET recently reported in literature are introduced. Also, muon-induced soft error is discussed focusing on the difference between positive and negative muons.

Reliability of 3D memories using Orthogonal Latin Square codes

Radiation is a cause of errors in electronics systems, especially on those deployed in space. Memories can suffer from different radiation effects including Single Event Upsets and Multiple Cell Upsets. These effects produce corruption of data and may cause a system malfunction. 3D die-stacked memories have been designed to increase bandwidth, reduce latency and limit power consumption. The shielding characteristic of the 3D structure causes a heterogeneous fault tolerance behaviour of the system where some of the inner dies are invulnerable while the outer dies require different protection levels. Orthogonal Latin Square codes are a class of error correcting codes that are modular and can provide different error correction degrees depending on the number of parity bits used. This paper proposed a solution based on current standards to provide dynamic and heterogeneous error correction capabilities to a 3D memory. To do so, Orthogonal Latin Square codes are used.

Multiple Cell Upsets Inside Aircrafts. New Fault-Tolerant Architecture

Multiple cell upsets (MCU) is an issue that has to be dealt with when designing electronics for working in a radiated environment. Furthermore, the constant evolution of ICs integration density causes an increment in the MCUs span. These issues are typical in aviation applications, where, additionally, fault-tolerant (FT) performance is required. FT systems are typically based on a redundancy concept for storing and retrieving healthy information, for example, with a triple modular redundancy (TMR) scheme. The main issue with redundancy is design oversizing. On the other hand, reconfiguration-based techniques allow error scrubbing with a limited overhead. The main drawback here is overhead vulnerability to radiation, which is invalid for FT requirements. This paper proposes a new hybrid architecture that takes advantage of the optimized performance of reconfiguration-based techniques supported on extremely compressed redundant information nonvulnerable to radiation, referred to in this paper as hardwired seed bits (HSB). It also includes different known techniques, such as interleaving, error detection and correction (EDAC) algorithms, etc., for optimizing the final architecture as much as possible. As a result, the proposed approach meets FT requirements thanks to nonvulnerable tiny redundant information combined with an optimized performance through EDAC-based implementation.

The orientational dependence of single event upsets and multiple-cell upsets in 65 nm dual DICE SRAM

The impact of different orientational angle of ion incidence on SEU and MCU are studied in dual DICE SRAM according to directionality of different sensitive pairs. The results show the worst orientational angle for SEU and MCU in dual DICE SRAM is incident with large tilting angle along the well even if nodal spacing of N/P sensitive pairs is the smallest. Ion tilt incidence with this orientational angle will greatly decrease SEU threshold and increase SEU cross section. At high LET, SEU saturation cross-sections in dual DICE design only has a small improvement by 40% over 6-T design whether ion incidence is normal or tilt due to charge sharing. Based on MCU topological pattern in dual DICE and 6-T design, the extent of charge diffusion and pararistic bipolar effect is quantified. Implications and application of the results for heavy ion SEU testing and RHBD technique in nanometer technology are presented.

Возникновение множественных сбоев под действием протонов в статических ОЗУ с технологической нормой 90 nm

AbstractThe occurrence of single-event upsets (SEUs) in 90-nm SRAM integrated circuits irradiated by 1000-MeV protons has been investigated. The experimental data were analyzed and processed, and the results showed the possibility of multiple cell upsets in the integrated circuits studied.

Multiple Cell Upset Injection in BRAMs for Xilinx FPGAs

On-chip block memories (BRAMs) in SRAM-based FPGAs store critical state information as well as user data which need to be protected against radiation-induced upsets. Therefore, reliability evaluation techniques and upset injection in system components are vital. Previous approaches to fault injection in BRAMs are limited in their abilities to create multiple cell upsets (MCUs) (and, in particular, a kind of MCU called multiple bit upsets) and are vulnerable to unintended state corruption in other memory elements when on-chip injectors are used. This letter proposes an efficient approach for multiple upsets emulation in BRAM contents exploiting the configuration memory cells responsible for initialization. The presented methodology ensures safe fault injection in BRAM contents while preserving the state of other memory elements of the design by using a one-time generated partial bitstream. The approach does not require the time-consuming bitstream generation process for every fault but rather uses run-time single-frame modifications for injection purposes.

Resistance-Based Modeling for Soft Errors in SOI SRAMs Caused by Radiation-Induced Potential Perturbation Under the BOX

Silicon-on-insulator (SOI) technology has been considered capable of developing devices with high tolerance against soft errors. In addition, with a thin buried oxide (BOX) layer, reduction in power consumption can be further achieved by applying a back bias from under the BOX, which is one of SOI technology’s many advantages and is appealing to Internet-of-Things and space applications. Recently, it was found during a heavy ion experiment that a static random access memory fabricated with a thin-BOX SOI technology exhibited a 100-fold soft error sensitivity when it received a back-bias. This was due to long line-type formation of multiple cell upsets (MCUs) caused by radiation-induced potential perturbation under the BOX. In this paper, a resistance-based model is developed for the evaluation of potential perturbation, predicting the device soft error sensitivity. The predictions made are verified by simulation. The model also provides an explanation to why the line-type MCU only occurs in a certain radiation environment and an optimization method to reduce the potential perturbation.

Multiple Upsets Induced by Protons in 90-nm SRAMs

The occurrence of single-event upsets (SEUs) in 90-nm SRAM integrated circuits irradiated by 1000-MeV protons has been investigated. The experimental data were analyzed and processed, and the results showed the possibility of multiple cell upsets in the integrated circuits studied.

Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications

Currently, faults suffered by SRAM memory systems have increased due to the aggressive CMOS integration density. Thus, the probability of occurrence of single-cell upsets (SCUs) or multiple-cell upsets (MCUs) augments. One of the main causes of MCUs in space applications is cosmic radiation. A common solution is the use of error correction codes (ECCs). Nevertheless, when using ECCs in space applications, they must achieve a good balance between error coverage and redundancy, and their encoding/decoding circuits must be efficient in terms of area, power, and delay. Different codes have been proposed to tolerate MCUs. For instance, Matrix codes use Hamming codes and parity checks in a bi-dimensional layout to correct and detect some patterns of MCUs. Recently presented, column–line–code (CLC) has been designed to tolerate MCUs in space applications. CLC is a modified Matrix code, based on extended Hamming codes and parity checks. Nevertheless, a common property of these codes is the high redundancy introduced. In this paper, we present a series of new low-redundant ECCs able to correct MCUs with reduced area, power, and delay overheads. Also, these new codes maintain, or even improve, memory error coverage with respect to Matrix and CLC codes.

Measurement and Mechanism Investigation of Negative and Positive Muon-Induced Upsets in 65-nm Bulk SRAMs

Irradiation experiments of positive and negative muon were conducted for 65-nm bulk CMOS static random-access memory. The experimental results reveal that parasitic bipolar action (PBA) contributes to negative muon-induced upsets. We observe an increase in single event upset (SEU) cross section at higher operation voltage under negative muon irradiation while positive muon shows an opposite decreasing tendency. Also, the proportion of multiple-cell upset (MCU) events to all the negative muon-induced upset events is up to 66, and more than a 20-bit MCU is observed. Furthermore, Monte Carlo simulation of particle and heavy ion transport code system (PHITS) is performed for explaining the difference in SEU between positive and negative muons. We also discuss the charge threshold that triggers PBA-induced MCU using measurement and simulation results with different momentum muons. The estimated threshold is much larger than the charge that the positive muons can deposit, which well explains that no PBA-induced MCUs are observed under positive muon irradiation.

The Impact of Multiple-Cell Charge Generation on Multiple-Cell Upset in a 20-nm Bulk SRAM

Single-event upsets induced by multiple-cell charge generation are studied in a 20-nm bulk SRAM by performing laser irradiation tests. The single-pulse two-photon absorption is utilized to simulate charge generation over multiple SRAM cells. The analysis of fail bit maps reveals that the physical topology of fail bits strongly depends on data patterns stored in SRAM cells. Our results indicate that potential perturbations in multiple p-wells play a key role in determining fail bit patterns. A novel multiple-cell upset mechanism, named multi-well coupled potential unbalancing, is proposed based on the consideration of the unbalanced activation of parasitic bipolar effects. The dominance of this mechanism is confirmed through multiple-pulse irradiation tests.

An Extensible Code for Correcting Multiple Cell Upset in Memory Arrays

As the microelectronics technology continuously advances to deep submicron scales, the occurrence of Multiple Cell Upset (MCU) induced by radiation in memory devices becomes more likely to happen. The implementation of a robust Error Correction Code (ECC) is a suitable solution. However, the more complex an ECC, the more delay, area usage and energy consumption. An ECC with an appropriate balance between error coverage and computational cost is essential for applications where fault tolerance is heavily needed, and the energy resources are scarce. This paper describes the conception, implementation, and evaluation of Column-Line-Code (CLC), a novel algorithm for the detection and correction of MCU in memory devices, which combines extended Hamming code and parity bits. Besides, this paper evaluates the variation of the 2D CLC schemes and proposes an additional operation to correct more MCU patterns called extended mode. We compared the implementation cost, reliability level, detection/correction rate and the mean time to failure among the CLC versions and other correction codes, proving the CLCs have high MCU correction efficacy with reduced area, power and delay costs.

Heavy ion-induced single event upset sensitivity evaluation of 3D integrated static random access memory

Heavy ion-induced single event upsets (SEUs) of static random access memory (SRAM), integrated with three-dimensional integrated circuit technology, are evaluated using a Monte Carlo simulation method based on the Geant4 simulation toolkit. The SEU cross sections and multiple cell upset (MCU) susceptibility of 3D SRAM are explored using different types and energies of heavy ions. In the simulations, the sensitivities of different dies of 3D SRAM show noticeable discrepancies for low linear energy transfers (LETs). The average percentage of MCUs of 3D SRAM increases from 17.2 to 32.95%, followed by the energy of 209Bi decreasing from 71.77 to 38.28 MeV/u. For a specific LET, the percentage of MCUs presents a notable difference between the face-to-face and back-to-face structures. In the back-to-face structure, the percentage of MCUs increases with a deeper die, compared with the face-to-face structure. The simulation method and process are verified by comparing the SEU cross sections of planar SRAM with experimental data. The upset cross sections of the planar process and 3D integrated SRAM are analyzed. The results demonstrate that the 3D SRAM sensitivity is not greater than that of the planar SRAM. The 3D process technology has the potential to be applied to the aerospace and military fields.

Analysis of multiple cell upset sensitivity in bulk CMOS SRAM after neutron irradiation

In our previous studies, we have proved that neutron irradiation can decrease the single event latch-up (SEL) sensitivity of CMOS SRAM. And one of the key contributions to the multiple cell upset (MCU) is the parasitic bipolar amplification, it bring us to study the impact of neutron irradiation on the SRAM’s MCU sensitivity. After the neutron experiment, we test the devices’ function and electrical parameters. Then, we use the heavy ion fluence to examine the changes on the devices’ MCU sensitivity pre- and post-neutron-irradiation. Unfortunately, neutron irradiation makes the MCU phenomenon worse. Finally, we use the electric static discharge (ESD) testing technology to deduce the experimental results and find that the changes on the WPM region take the lead rather than the changes on the parasitic bipolar amplification for the 90 nm process.

Anomalous annealing of floating gate errors due to heavy ion irradiation

Abstract Using the heavy ions provided by the Heavy Ion Research Facility in Lanzhou (HIRFL), the annealing of heavy-ion induced floating gate (FG) errors in 34 nm and 25 nm NAND Flash memories has been studied. The single event upset (SEU) cross section of FG and the evolution of the errors after irradiation depending on the ion linear energy transfer (LET) values, data pattern and feature size of the device are presented. Different rates of annealing for different ion LET and different pattern are observed in 34 nm and 25 nm memories. The variation of the percentage of different error patterns in 34 nm and 25 nm memories with annealing time shows that the annealing of FG errors induced by heavy-ion in memories will mainly take place in the cells directly hit under low LET ion exposure and other cells affected by heavy ions when the ion LET is higher. The influence of Multiple Cell Upsets (MCUs) on the annealing of FG errors is analyzed. MCUs with high error multiplicity which account for the majority of the errors can induce a large percentage of annealed errors.

Multiple-Cell Upsets Induced by Single High-Energy Electrons

Multiple-cell upsets (MCUs) in static random access memory-based field-programmable gate arrays from three different technology nodes are recorded from single-particle interactions with 20–52 MeV electrons. Indirect ionization events associated with an electronuclear reaction are shown to be the cause of the MCUs. As has been observed with other ionizing particles such as heavy ions and neutrons, the electron upset cross section per bit is shown to decrease with smaller technology nodes, but the prevalence of electron-induced MCUs increases with scaling.

Laser Visualization of the Development of Long Line-Type Mutli-Cell Upsets in Back-Biased SOI SRAMs

An interesting multiple-cell upset (MCU) phenomenon in silicon-on-insulator (SOI) static random access memorys (SRAMs) featuring long lines of more than ten flipped cells is studied. Such an abnormal MCU phenomenon was recently observed for back-biased SOI SRAMs in a heavy-ion test. Using a two-photon absorption-based laser system, we performed fixed-point observations and visualized the development of long line-type MCUs with increasing back bias. The visualization results provided insights to elucidate the mechanism behind these phenomena. Furthermore, using fixed-point observations, we extracted the length of MCUs for various bias conditions and laser strike positions. It was found that for all cases studied, the line length could be explained using an analytical model.