Multiple Cell Upsets Research Articles

Formal Analysis of Multiple-Cell Upset Failure Based on Common Cause Failure Theory

As an important component of space electronic systems, static random-access memory based field programmable gate arrays (FPGAs) are inevitably affected by single-event upsets, including single-cell upset (SCU) and multiple-cell upset (MCU), caused by space radiation. In particular, as the technology scales down, the probability of MCU increases significantly; however, the analysis of MCU remains an open challenge. Based on the common cause failure theory and continuous-time Markov chain, this article proposes a new hybrid model to quantify the coexistence effect of MCU and SCU on mitigation design modes with different combinations of strategies, such as triple modular redundancy, partition, and scrubbing. Synchronization and interleaving modeling technologies are used to construct the concurrent behavior of an FPGA system under different mitigation strategies and MCU problems. In addition, we introduce a partition factor to quantitatively explain the phenomena and laws of MCUs acting on adjacent partitions. The proposed method is demonstrated using TMR with scrubbing and partition strategies, which verify that the existence of MCU reduces the system reliability and availability, and the scrubbing and partition strategy are effective against MCU issues. More importantly, the limitations of mitigation strategies in different occurrence probabilities of MCU can be found by the proposed method. In summary, the analysis and discussion presented in this article can provide useful insights for relevant designers to select and optimize different design patterns of a system operating in a dynamic and complex radiation environment.

Analysis of multiple cell upset characteristics for logical circuits in radiation environment

With the design and fabrication of integrated circuits entering the deep submicron and nano-scale era, the possibility of radiation inducing multiple cell upsets (MCU) increases noticeably. Extracting MCU characteristics from the observed upsets can provide useful information for designing hardening strategies and fault injection experiments. This paper reports the analysis of MCU characteristics for logical circuits in radiation environment, using mathematical statistics. MCU feature extraction was extended from storage circuits to logical circuits. Gaussian distribution was proposed, verified and implemented in MCU study to describe the condition when MCU dominates (the number of upsets in single event is mostly larger than 1). In this way, MCU characteristics in logical circuits can be analyzed, including both upsets due to cells and burst upsets due to global resources.

Single Event Upsets Under 14-MeV Neutrons in a 28-nm SRAM-Based FPGA in Static Mode

A sensitivity characterization of a Xilinx Artix-7 field programmable gate array (FPGA) against 14.2-MeV neutrons is presented. The content of the internal static random access memories (SRAMs) and flip-flops was downloaded in a PC and compared with a golden version of it. Flipped cells were identified and classified as cells of the configuration RAM, block RAM (BRAM), or flip-flops. Single bit upsets (SBUs) and multiple cell upsets (MCUs) with multiplicities ranging from 2 to 8 were identified using a statistical method. Possible shapes of multiple events are also investigated, showing a trend to follow wordlines. Finally, MUlti-Scales Single Event Phenomena Predictive Platform (MUSCA SEP3) was used to make assessment of actual environments and an improvement of single event upset (SEU) injection test is proposed.

Low-Energy Protons—Where and Why “Rare Events” Matter

Failures (or upsets) of complementary metal-oxide-semiconductor (CMOS) devices, due to direct ionization from protons, were first predicted in 1982 and subsequently realized in 2007 for low-energy (1 MeV) protons (LEPs). For terrestrial applications, secondary LEPs, generated during collision events, may cause upsets, especially in cells far away from the initial strike location than their heavier spallation-fragment cousins. However, direct ionization may be more important in space and high-altitude environments due to the large flux of primary high-energy protons impinging on nearby spacecraft (and local device) shielding. In this article, a brief review of the relevant literature will be followed by a discussion of the sensitivity to direct ionization of typical CMOS devices. It will be shown that a significant number of LEPs are generated by cosmic radiation spallation events, suggesting that track structures and exact device hit locations need to be understood and effectively modeled, especially for modern devices. Also, the rate of multiple cell upsets, and hence multiple bit upsets, in these environments will be explored, with possible mitigation techniques discussed. The published work on muons and delta electrons, in addition to LEPs, will be reviewed as potential single-event upset (SEU) sources with the future scaling of CMOS devices.

Characterization of Single Event Cell Upsets in a Radiation Hardened SRAM in a 40 nm Bulk CMOS Technology

A large amount of data needs to be stored in integrated circuits when data are being processed. The integrated circuits contain a large amount of static random access memory (SRAM) due to its high level of integration and speed. SRAM units should be as small as possible to achieve higher storage density. In this work, the features of single cell upsets (SCUs) and multiple cell upsets (MCUs) in a full custom SRAM are tested for a 40 nm bulk CMOS technology node, and Ge (linear energy transfer (LET) = 37.3 MeV cm2/mg), Cl (LET = 13.1 MeV cm2/mg), Al (LET = 8.6 MeV cm2/mg), O (LET = 3.1 MeV cm2/mg), and Li (LET = 0.5 MeV cm2/mg) particles are used. The test results show that the total single cell upset events are 2,000,147, 1,124,269, 413,100, 311,311, and 47,815 under the irradiation of Ge, Cl, Al, O, and Li, respectively. Moreover, due to single event upset reversal mechanism, multiple cell upsets significantly decrease. The total multiple cell upset events are 10, 4, 0, 0, and 0 under the irradiation of Ge, Cl, Al, O, and Li, respectively. There are a lot of single cell upsets appearing under Ge, Cl, Al, O, and Li exposure. The number is increasing with increasing LET, which means that well contacts still need optimization in the full custom SRAM. Close spacing of well contacts or increasing contacts are the approaches used to drain the excess carriers quickly, and error detection and correction (EDAC) is used for SRAM technology. The features show that SCUs have become a major source of soft errors for the full custom SRAM. Combining close spacing of well contacts with error detection and correction (EDAC) and a well engineering scheme are used to reduce single cell upsets, although there are a few MCUs which are inevitable. Radiation hardened by design schemes needs to be further improved.

Analytical reliability estimation of SRAM-based FPGA designs against single-bit and multiple-cell upsets

This paper addresses the problem of hardware tasks reliability estimation in harsh environments. A novel statistical model is presented to estimate the reliability, the mean time to failure, and the number of errors of hardware tasks running on static random-access memory (SRAM)-based partially run-time reconfigurable field programmable gate arrays (FPGAs) in harsh environments by taking both single-bit upsets and multiple-cell upsets into account. The model requires some features of the hardware tasks, including their computation time, size, the percent of critical bits, and the soft error rates of k-bit events (k ≥ 1) of the environment for the reliability estimation. Such an early estimation helps the developers to assess the reliability of their designs at earlier stages and leads to reduce the development cost. The proposed model has been evaluated by conducting several experiments on actual hardware tasks over different environmental soft error rates. The obtained results, endorsed by the 95% confidence interval, reveal the high accuracy of the proposed model. When comparing this approach with a reliability model (developed by the authors in a previous work) that does not consider the occurrence of multiple-cell upsets, an overestimation of the mean time to failure of 2.88X is observable in the latter. This points to the importance of taking into account multiple events, especially in modern technologies where the miniaturization is high.

Lower complexity error location detection block of adjacent error correcting decoder for SRAMs

Multiple cell upsets (MCUs) caused by radiation is an important issue related to the reliability of embedded static random access memories (SRAMs). Multiple random and adjacent error correcting codes have been extensively employed for several years to protect stored data in SRAMs against MCUs. A compact and fast error correcting codec is desirable in most of these applications. In this study, simplified expressions for error location detection (ELD) block for single error correction-double error detection-double adjacent error correction (SEC-DED-DAEC) and single error correction-double error detection-triple adjacent error correction (SEC-DED-TAEC) decoders have been obtained by employing Karnaugh map. The conventional SEC-DED-DAEC and SEC-DED-TAEC decoders have been designed and implemented in both field-programmable gate array and ASIC platforms by considering these simplified ELD expressions. In FPGA platform, the proposed design for SEC-DED-DAEC and SEC-DED-TAEC decoders require 1.37–28.40% improvement in area and maximum 14.74% improvement in delay compared to existing designs. Whereas ASIC-based designs provide 2.20–26.81% reduction in area and 0.30–28.96% reduction in delay compared to existing related works. So the proposed design can be considered as an efficient alternative of traditional adjacent error correcting decoders in resource constraint applications.

Angular Sensitivity of Neutron-Induced Single-Event Upsets in 12-nm FinFET SRAMs With Comparison to 20-nm Planar SRAMs

The angular sensitivity of neutron-induced single-event upsets (SEUs) is studied in 12-nm FinFET SRAMs. Irradiation experiments are performed using a terrestrial environment-compatible source with varying incidence angles. The analyses of the occurrence rates of SEUs and multiple-bit upsets (MBUs) demonstrate that although the SEU rate decreases at grazing incidence, the MBU rate increases when the incidence direction is parallel to the word lines (WLs) of the SRAM array, as similarly observed in our previous experiments for 20-nm planar SRAMs. It is found that the angular response of multiple-cell upsets (MCUs) is different between the 12-nm FinFET and 20-nm planar SRAMs. The comparative analysis of the voltage dependence of the MCU ratio reveals that this difference is due to the different contribution of parasitic bipolar effects (PBEs), which are more significant in the 20-nm planar SRAMs. It is also indicated that in the 12-nm FinFET SRAMs, the contribution of PBEs is relatively large when the incidence angle is parallel to the WLs. Through the characterization of the MCU events, the validity of this picture is confirmed based on the voltage dependence of the pattern-wise MCU ratio with the consideration of the impact of PBEs on fail bit patterns.

Optimized buffer protection for network-on-chip based on Error Correction Code

Newest technologies of integrated circuits manufacture require a communication architecture such as a Network-on-Chip (NoC). The NoC buffers are susceptible to Multiple Cell Upsets (MCU). Besides, as the technology scales down, the probability of MCU increases. Thus, applying an Error Correction Code (ECC) in NoC buffers may come as a solution for reliability issues, although increasing the design costs and requiring a buffer with higher storage capacity. This work evaluates two models of data arrangement for NoC buffers protected by three types of ECCs, preserving the protection of the storage information, and reducing the area usage and power dissipation compared to other solutions. We evaluated the performance of fault-tolerant NoC buffer schemes by applying the models on three types of ECC and measuring the buffer area, power overhead and error coverage. The experimental results show that the use of the Optimized model keeps the reliability for MCU while reducing area consumption and power dissipation in approximately 25% and 30%, respectively.

A Statistical Method for MCU Extraction Without the Physical-to-Logical Address Mapping

A statistical method was proposed to extract multiple-cell upsets (MCUs) from single-event upsets (SEUs) without the physical-to-logical address mapping of the device under test (DUT). The method was first developed to extract the mapping relation between the least significant bits (LSBs) of the physical address and the logical address bits. Then, the mapping relation was utilized to extract MCUs from the SEUs. Using the proposed method, the proportion, size, and shape of the MCU can be obtained with high accuracy. To evaluate the proposed statistical method, the method was applied to SEU test data of a 0.18-μm static random-access memory (SRAM) irradiated by various heavy ions. The results demonstrated its effectiveness in MCU extraction.

Inherent Uncertainty in the Determination of Multiple Event Cross Sections in Radiation Tests

In radiation tests on SRAMs or field-programmable gate arrays (FPGAs), two or more independent bitflips can be misled with a multiple event if they accidentally occur in neighbor cells. In the past, different tests, such as the “birthday statistics,” have been proposed to estimate the accuracy of the experimental results. In this article, simple formulas are proposed to determine the expected number of false 2- and 3-bit multiple cell upsets (MCUs) from the number of bitflips, memory size, and the method used to search multiple events. These expressions are validated using the Monte Carlo simulations and experimental data, and a technique is proposed to refine the experimental data and thus partially removing possible false events. Finally, it is demonstrated that there is a physical limit to determine the cross section of memories with arbitrary accuracy from a single experiment.

Extended Matrix Region Selection Code: An ECC for adjacent Multiple Cell Upset in memory arrays

With the widespread of electronics nowadays, Single Event Effects (SEEs) have become a significant concern, not only for critical applications like aerospace and military but also for the automotive industry and medical instruments, where reliability is always at a premium. This concern is notable in environments containing ElectroMagnetic (EM) and ionizing radiations, whose interactions with the matter may change the state of memory elements and thus, degrading system reliability. Technology scaling down increases the probability that the strike of a charged particle or a power bus fluctuation due to conducted EM interference affects more than one cell; therefore, resulting in a Multiple Cell Upset (MCU). Single Error Correction–Double Error Detection (SEC-DED) codes are among the most applied techniques to provide reliability to memory systems. However, standard implementations of SEC-DED codes are not suitable anymore to provide information reliability because they cannot satisfactorily handle a considerable number of bit-flips per coded word, i.e., MCU occurrence. In this context, this paper proposes the extended Matrix Region Selection Code (eMRSC), an improved version of MRSC, which extends the original 16-bit code previously published to a new MRSC version of 32 data bits. Additionally, it is proposed a new scheme of data matrix regions for reducing the number of generated redundant bits. The proposed codes were compared to well-known codes, presenting outperforms in all experiments. The synthesis analysis showed that the proposed codes are not only reliable, but they also result in low implementation cost (i.e., low area, coding/decoding delay and power overheads).

Experimental study on neutron single event effects of commercial SRAMs based on CSNS

The experiment of neutron single event effect was carried out at China Spallation Neutron Source (CSNS) back-n on 13 kinds of commercial SRAM. The single event upset (SEU) cross section of each device was obtained, and multiple cell upsets (MCU) were extracted from the SEUs using a statistical method without layout information. The influences of the test pattern, feature size and device layout on the SEU cross section and MCU were studied. The results show that the test pattern has little influence on the SEU cross section of the devices, but has a great influence on the MCU ratio of some devices. The feature size has influence both on the SEU cross section and the MCU ratio of the devices. The influence on SEU cross section is not definite. The influence on the MCU ratio is definite. Both the ratio and the maximum size of the MCUs increase with the decrease of the feature size. The difference of layout has great influence both on the SEU cross section and the MCU ratio of the device. In addition, compared with the results of plateau irradiation, the ratio of MCU in CSNS back-n is less than that of plateau irradiation. There are two reasons for this difference. One is that the energy spectrum of CSNS back-n is softer than that of the atmospheric neutron. The other is the neutron beam at CSNS back-n is perpendicular to the device under test. Therefore, evaluating the atmospheric neutron SEE using CSNS back-n line may underestimate the MCU ratio of the device under test. The experimental data, analytical methods and results obtained in this paper are valuable for the researchers to carry out the atmospheric neutron SEE test and the evaluation of devices on atmospheric neutron SEE.

DESIGN AND DEVELOPMENT OF ENHANCED MEMORY RELIABILITY AGAINST MULTIPLE CELL UPSETS USING DMC

Transient multiple cell upsets (MCUs) are beginning to seriously affect the reliability of memories when they are exposed to radiation settings. More complex error correction codes (ECCs) are often used to protect memory and prevent data corruption caused by MCUs; nevertheless, their primary drawback is an increase in delay overhead. Recently, matrix codes (MCs) based on Hamming codes have been proposed for memory protection. The two error correction codes and the fact that not all situations lead to an improvement in mistake correction skills are the main issues. This work proposes a revolutionary decimal matrix code (DMC) based on the divide-symbol to provide better memory reliability with minimal delay overhead. The proposed DMC uses the decimal algorithm to provide the maximum amount of error detection capability. Furthermore, to minimize the area overhead of extra circuits without interfering with the encoding and decoding processes, it is advised to implement the encoder-reuse method (ERT)

Statistical Method to Extract Radiation-Induced Multiple-Cell Upsets in SRAM-Based FPGAs

Radiation-induced multiple-cell upsets (MCUs) are a concern because they can overcome the protection of error correction code and triplicated designs. Extracting MCU data from radiation tests is helpful to perform more accurate fault injection tests, where MCUs could be simulated with the injection of bits based on the MCUs shapes, sizes, and frequencies. This article presents a statistical method to extract MCU shapes and frequencies from components with no information regarding their physical layout. The proposed method can be used to extract MCU information from BRAM and CRAM alike. The results show the MCU data for three families of Xilinx field-programmable gate arrays (FPGAs).

Understanding the Difference in Soft-Error Sensitivity of Back-Biased Thin-BOX SOI SRAMs to Space and Terrestrial Radiation

High tolerance against soft errors is regarded as one of the advantages of silicon-on-insulator (SOI) technology, as well as the reduction in power consumption by applying a back-bias from under the buried oxide layer (BOX). These advantages are appealing to Internet-of-Things (IoT) and space applications. Recently, it was found in a heavy-ion experiment that a static random-access memory (SRAM) fabricated with a 65-nm thin-BOX SOI technology exhibited a 100-fold soft-error sensitivity when it received a back-bias. This was due to long line-type formations of multiple cell upsets (MCUs) caused by radiation-induced potential perturbation under the BOX. However, devices fabricated with a similar technology tested with terrestrial neutrons did not show such a phenomenon in another previous study. To understand this difference, in the present work, a resistance-based model is adopted. Prediction of device soft-error sensitivity due to line-type MCUs under different radiation environment are also made. Then, characteristics of secondary ions generated by terrestrial neutrons in silicon devices are studied using simulation.

Real-time soft error testing system for large-area QDR II+ SRAM array on the Tibetan Plateau

In this study, a real-time testing system consisting of a large-area array of 72 QDR II+ SRAMs (larger than 10-Gbit manufactured in 65 nm CMOS technology) was developed and assembled on the Tibetan Plateau at an altitude of 4300 m. A new topological structure with 9 QDR II+ devices operating synchronously by a single FPGA was proposed and the signal integrity of the large-area high-speed QDR II+ SRAMs was solved. Under harsh natural radiation conditions, the complex and expensive system monitored a large number of devices in parallel for 153 days uninterruptedly. 43 soft errors including single bit upsets (SBUs), multiple-cell upsets (MCUs), single event induced hard errors (SHEs) and burst errors were observed, with a calculated SER value of 2356 FIT/Mb. Meanwhile, these results effectively validated the testing system.

Improved hybrid scrubbing scheme for spaceborne static random access memory‐based field programmable gate arrays

With the shrinking feature sizes of static random access memory-based field programmable gate arrays (FPGAs), the occurrence probability of multiple-cell upsets (MCUs) in FPGAs continues to increase. This reduces the reliability of FPGAs. This article proposes an improved hybrid scrubbing scheme to solve this problem. Based on the conventional hybrid scrubbing scheme, the error detection process is improved by changing the error correction object from an erroneous frame to an erroneous zone. MCUs can be rapidly corrected through continuous error detection and erroneous zone correction. The theoretical analysis and implementation results show that the improved hybrid scrubbing scheme can effectively reduce the average repair time of MCU errors.

Similarity Analysis on Neutron- and Negative Muon-Induced MCUs in 65-nm Bulk SRAM

Multiple-cell upset (MCU) in static random access memory (SRAM) is a major concern in radiation effects on very large scale integration (VLSI) since it can spoil error correcting codes (ECCs). Neutron-induced MCUs have been characterized for terrestrial environment. On the other hand, negative muon-induced MCUs, which are caused by secondary ions generated through muon capture process, were recently reported. Neutron- and negative muon-induced MCUs are both caused by secondary ions, and hence, they are expected to have some similarity. In this paper, we compare negative muon- and neutron-induced MCUs in 65-nm bulk SRAMs at the irradiation experiments using spallation and quasi-monoenergetic neutrons and monoenergetic negative muons. The measurement results show that the dependencies of MCU event cross section on operating voltage are almost identical. The high operating voltage makes both negative muon- and neutron-induced MCU cross sections larger due to parasitic bipolar action. Consequently, large-bit MCUs are observed under the irradiation using both neutrons and muons. On the other hand, at 0.4 V, neutrons induce larger-bit MCUs (> 12 bits) whereas negative muons cause up to 11-bit MCUs. Upsets of 3 or larger bits along word line (WL) are observed at spallation neutron beams. To explain the similarity of MCUs induced by neutrons and negative muons, the Monte Carlo simulation is conducted to investigate the deposited charge. The distributions of deposited charge obtained by the simulation are consistent with the above-mentioned experimental observations.

Tibetan-Plateau-Based Real-Time Testing and Simulations of Single-Bit and Multiple-Cell Upsets in QDRII+ SRAM Devices

Real-time soft error rate of 65-nm QDRII+ static random access memory was measured on the Tibetan-plateau with an altitude of 4300 m. Error types including single-bit upset (SBU), multiple-cell upset (MCU), and burst errors were observed. The MCU ratio is 23%, with a maximum size of nine cells. Majority of the MCU events are vertically oriented along the well stripes. Monte Carlo simulations were further performed to study the characteristics of the neutron-induced secondary ions. Diverse secondary ion species, from the proton to Re, were found, which were significantly affected by the presence or absence of the tungsten layer. The impact of neutron energy on the linear energy transfer (LET), range, and deposited charge of secondary ions in the sensitive volume was revealed.