Multilevel Cell Capability Research Articles

Organic-inorganic FAPbBr3 perovskite based flexible optoelectronic memory device for light-induced multi level resistive switching application

Herein, we report the multilevel resistive switching memory performance of the fabricated Al/FAPbBr3/ITO structure. The device exhibited bipolar RS behaviour with excellent electrical performances such as no forming process, low operating voltages, low power consumption, good stability and a high ON/OFF ratio (∼103). The device also showed the multilevel cell capability which was achieved by delicate control over compliance current and the stopping voltage. Owing to the rising demand for flexible devices, the constancy and uniformity of the RS behaviour of our fabricated device with mechanical robustness were confirmed by examining the memory performance of the device under various bending conditions. Besides, the device exhibited photo response-ability for which the RS effect can be enhanced by light irradiation. This investigation may be explored in the data encoding process with a certain wavelength of incident light. Intrinsic phenomena of RS effect have been explained by the growth and rupture of electric field-induced reproducible conducting filaments formed by halide vacancies as well as active Al atoms. This work provides a way for exploring the organic-inorganic hybrid perovskites nanocrystals for the development of next-generation low power consumption, light-assisted, flexible volatile memory devices.

Improved multilevel storage capacity in Ge2Sb2Te5-based phase-change memory using a high-aspect-ratio lateral structure

Further improvement of storage density is a key challenge for the application of phase-change memory (PCM) in storage-class memory. However, for PCM, storage density improvements include feature size scaling down and multi-level cell (MLC) operation, potentially causing thermal crosstalk issues and phase separation issues, respectively. To address these challenges, we propose a high-aspect-ratio (25:1) lateral nanowire (NW) PCM device with conventional chalcogenide Ge2Sb2Te5 (GST-225) to realize stable MLC operations, i.e., low intra- and inter-cell variability and low resistance drift (coefficient = 0.009). The improved MLC performance is attributed to the high aspect ratio, which enables precise control of the amorphous region because of sidewall confinement, as confirmed by transmission electron microscopy analysis. In summary, the NW devices provide guidance for the design of future high-aspect-ratio three-dimensional PCM devices with MLC capability.

Ternary Arithmetic Logic Unit Design Utilizing Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM).

Due to the difficulties associated with scaling of silicon transistors, various technologies beyond binary logic processing are actively being investigated. Ternary logic circuit implementation with carbon nanotube field effect transistors (CNTFETs) and resistive random access memory (RRAM) integration is considered as a possible technology option. CNTFETs are currently being preferred for implementing ternary circuits due to their desirable multiple threshold voltage and geometry-dependent properties, whereas the RRAM is used due to its multilevel cell capability which enables storage of multiple resistance states within a single cell. This article presents the 2-trit arithmetic logic unit (ALU) design using CNTFETs and RRAM as the design elements. The proposed ALU incorporates a transmission gate block, a function select block, and various ternary function processing modules. The ALU design optimization is achieved by introducing a controlled ternary adder–subtractor module instead of separate adder and subtractor circuits. The simulations are analyzed and validated using Synopsis HSPICE simulation software with standard 32 nm CNTFET technology under different operating conditions (supply voltages) to test the robustness of the designs. The simulation results indicate that the proposed CNTFET-RRAM integration enables the compact circuit realization with good robustness. Moreover, due to the addition of RRAM as circuit element, the proposed ALU has the advantage of non-volatility.

Three Resistance States Achieved by Nanocrystalline Decomposition in Ge‐Ga‐Sb Compound for Multilevel Phase Change Memory

AbstractPhase‐change memory (PCM), using the fast and reversible transition between crystal and glass to store binary data, is a promising candidate for next‐generation information storage and computing technologies. Recording more than one bit of information on each memory cell, known as multilevel cell (MLC) technology, can greatly increase the data density of PCMs. In this paper, the MLC capability in a phase change material Ge‐Ga‐Sb (GGS) is explored. Using the “SET” operation with increasing voltage amplitudes on this PCM cell in a 250 nm pillar structure device, three resistance levels are achieved and can be stabilized within large operating voltage windows, allowing large tolerance of SET voltage variation which may lead to the overlap of the neighboring resistance levels. It is discovered that the additional resistance level other than “0” and “1” is enabled by compositional phase separation in the nanocrystalline GGS, as revealed via atom probe tomography and electronic microscopy. The device also shows small resistance drift (ν = 0.025) in amorphous state, about four times lower than prototypical Ge‐Sb‐Te‐based PCMs, stabilizing it against time variation. Meanwhile, high thermal stability (Tc ≈ 300 °C) in GGS‐based device can also facilitate the practical applications in some extreme conditions.

Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM) Based Ternary Combinational Logic Circuits

The capability of multiple valued logic (MVL) circuits to achieve higher storage density when compared to that of existing binary circuits is highly impressive. Recently, MVL circuits have attracted significant attention for the design of digital systems. Carbon nanotube field effect transistors (CNTFETs) have shown great promise for design of MVL based circuits, due to the fact that the scalable threshold voltage of CNTFETs can be utilized easily for the multiple voltage designs. In addition, resistive random access memory (RRAM) is also a feasible option for the design of MVL circuits, owing to its multilevel cell capability that enables the storage of multiple resistance states within a single cell. In this manuscript, a design approach for ternary combinational logic circuits while using CNTFETs and RRAM is presented. The designs of ternary half adder, ternary half subtractor, ternary full adder, and ternary full subtractor are evaluated while using Synopsis HSPICE simulation software with standard 32 nm CNTFET technology under different operating conditions, including different supply voltages, output load variation, and different operating temperatures. Finally, the proposed designs are compared with the state-of-the-art ternary designs. Based on the obtained simulation results, the proposed designs show a significant reduction in the transistor count, decreased cell area, and lower power consumption. In addition, due to the participation of RRAM, the proposed designs have advantages in terms of non-volatility.

Low power high speed 3-bit multilevel resistive switching in TiO2 thin film using oxidisable electrode

Multilevel cell (MLC) capability of a memory device is an attractive alternative to realise high integration density of memory arrays. In addition, power efficient memory cell along with MLC capability has huge potential in neuromorphic computing and data storage applications. In this study low power, high speed and 3-bit multilevel bipolar resistance switching operation is reported in TiO2 thin films where copper is used as counter electrode. On account of using an oxidisable electrode, low programming voltages (∼+0.2 V, −0.1 V) along with low reset current (∼10 µA) are observed, thereby ensuing low power (∼µW) memory operation. Additionally, observation of fast switching (∼250 ns) translated to ultra-low energy (∼pJ) consumption. By varying compliance current (IC) from 25 µA to 1.6 mA during the set process, eight distinct non-volatile resistance states are reliably obtained, which showed statistically significant and non-overlapping resistance distribution. The multilevel resistive switching in Cu/TiO2/Pt device is explained by considering filamentary the widening phenomenon in the electrochemical metallization memory cell. Numerical calculations revealed that increase in the diameter of the metallic conducting filament from ∼3 nm to 70 nm with increasing IC is accountable for multiple low resistance states. The results of this study are promising towards realisation of emerging memory devices with low operating power, fast switching operation and high spatial density.

Memory Performance of a Simple Pr0.7Ca0.3MnO3-Based Selectorless RRAM

Enhancement of nonlinearity (NL) in low-resistance state (LRS) currents of resistance random access memory (RRAM) devices is a key challenge for the selectorless RRAM array. The conventional approach is based on adding multiple dielectrics, e.g., tunnel layers to enable NL at the expense of stack simplicity. In this brief, we present a Pr0.7Ca0.3MnO3 (PCMO)-based selectorless RRAM device that exhibits high NL. The presented single oxide layer device (W/PCMO/Pt) enables selectorless RRAM without an extra tunnel barrier layer. The demonstrated device is forming free. It shows a low SET current density ( 104 A/cm2) and a high NL in LRS current for READ operation ( 105±5 ) and for SET operation ( 44±4 ) along with a large memory window (160±2) in dc cycling. Further, the device shows very low device-to-device variability $ ( {\sigma } / \mu along with excellent retention (ten years at 200 °C), good pulsed endurance (no degradation for >104 cycles), and a possible multilevel cell capability. A self-heating-based sharp current increase produces the NL to enable selectorless operation. Thus, a selectorless PCMO-based RRAM based on a novel mechanism is presented and benchmarked against the literature.

A 58-nm 2-Gb MLC “B4-Flash” Memory with Flexible Multisector Architecture

A 58-nm 2-Gb multi-level cell (MLC) B4-Flash memory with flexible multisector architecture has been developed, which can be realized by unique features of B4-Flash with P-channel cell; large-data programming with small cell current thanks to back bias-assisted band-to-band tunneling-induced hot electron (B4-HE) injection mechanism, simple erase sequence without over-erase problem. In this architecture, each program and erase unit size can be extended from 256 B to 4 KB and from 256 KB to 4 MB, respectively, by utilizing 8 sectors & 2 banks simultaneous operation, and consequently 10 times faster 3.7 MB/s rewrite speed than that of conventional NOR flash can be realized by 4 KB / 980 $\mu \text{s}$ programming and 4 MB / 80 ms erasing. A fast 110-ns random access with enough read margin has been achieved by simultaneous parallel sensing at 3 op-amps with cell-bias compensation scheme. This paper proves that B4-Flash can be a candidate for various applications which need both fast rewrite speed and fast random access as a fast rewritable NOR-type flash with MLC capability and scalability.

Domain Wall Magnets for Embedded Memory and Hardware Security

Domain wall memory (DWM) is one possible candidate for embedded cache application due to its multi-level cell capability, low standby power, fast access time, good endurance, and good retention. In this paper, we utilize a physics-based model of domain wall to comprehend the process variations and Joule heating that can lead to functional issues in the memory. We propose techniques to mitigate the impact of variability and Joule heating while enabling low-power and high-frequency operation. We show that the process variations in the nanowire (NW) is not good towards robustness, but it can be very useful for device authentication. We propose physically unclonable functions (PUFs) that exploit the nonlinear DW-dynamics for secure key generation. Two flavors of PUF designs are described namely relay-PUF and memory-PUF with lower overhead and power as compared to a traditional CMOS-PUFs and offer a higher degree of resilience against cloning.

A Model for Multilevel Phase-Change Memories Incorporating Resistance Drift Effects

Phase change memories are emerging as a most promising technology for future nonvolatile, solid-state, electrical storage. However, to compete effectively in mainstream storage applications, a multilevel cell capability is most desirable. Unfortunately, phase-change memories exhibit a temporal drift in programmed resistance (and in threshold switching voltage) which appears to be a fundamental and universal property of the amorphous or partially amorphous phase. Phase-change device models should therefore include these drift effects in a realistic way so that circuit and systems designers can assess the likely performance of multilevel phase-change memories in a variety of potential applications. In this paper, therefore, we present a comprehensive SPICE-based model for phase-change devices that includes the capability for programming into multiple resistance levels, the prediction of the drift of cell resistance (and threshold voltage) with time, and the capability for modeling the randomness inherent to the resistance drift phenomenon. Simulations of multilevel programming and drift phenomena using the model are presented and compared to experimental results, with which there is very good agreement.

Probabilistically Programmed STT-MRAM

Novel memory programming methods and corresponding memory structures are presented in this paper. Unlike conventional memory programming, this programming technique does not require deterministic switching of memory elements. This technique explicitly exploits the probabilistic switching characteristics of memory elements such as spin-transfer torque magnetic tunnel junction (STT-MTJ) to reduce programming power and delay. This technique also allows multilevel cell (MLC) spin-transfer torque magnetoresistive random access memory (STT-MRAM) to be fabricated with existing STT-MTJ fabrication processes, thus making high capacity STT-MRAM chips readily achievable. The optimal STT-MTJ switching probabilities are given in this paper for reaching minimum programming delay, power, and iteration. Moreover, this paper proves, by applying probabilistic programming to existing STT-MTJs, both programming delay and power can be reduced to levels beyond the reach of conventional deterministic programming. Furthermore arbitrarily small programming bit error rate (BER) can be accomplished in theory using probabilistic programming without much penalty on average programming delay and power. On the contrary, deterministic programming always presents finite programming BER, which is expensive to reduce in terms of programming power and delay. The MLC capability of STT-MTJ clusters has also been confirmed using fabricated STT-MTJ devices. The major circuitries for implementing probabilistically programmed MLC STT-MRAM are also presented in this paper.

A Bipolar-Selected Phase Change Memory Featuring Multi-Level Cell Storage

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> In this paper, a 90-nm 128-Mcell non-volatile memory based on phase-change <formula formulatype="inline"><tex Notation="TeX">${\hbox{Ge}}_{2}\mathchar"707B {\hbox{Sb}}_{2}\mathchar"707B {\hbox{Te}}_{5}$</tex></formula> alloy is presented. Memory cells are bipolar selected, and are based on a <formula formulatype="inline"> <tex Notation="TeX">$\mu{\hbox{trench}}$</tex></formula> architecture. Experimental investigation on multi-level cell (MLC) storage is addressed exploiting the chip MLC capability. To this end, a programming algorithm suitable for 2 bit/cell storage achieving tightly placed inner states (in terms of cell current or resistance) is proposed. Measurements showed the possibility of placing the required distinct cell current distributions, thus demonstrating the feasibility of the MLC phase-change memory (PCM) storage concept. Endurance tests were also carried out. Cumulative distributions after 2-bit/cell programming before cycling and after 100 k program cycles followed by 1 h/150<formula formulatype="inline"> <tex Notation="TeX">$\,^{\circ}{\hbox{C}}$</tex></formula> bake are presented. Experimental results on MLC endurance are also provided from a 180-nm 8-Mb PCM demonstrator with the same <formula formulatype="inline"><tex Notation="TeX">$\mu{\hbox{trench}}$</tex> </formula> cell structure. </para>

Bipolar and Unipolar Resistive Switching in Cu-Doped $ \hbox{SiO}_{2}$

Scalable nonvolatile memory devices that operate at low voltage and current, exhibit multilevel cell capability, and can be read nondestructively using simple circuitry, are highly sought after. Such devices are of particular interest if they are compatible with back-end-of-line processing for CMOS integrated circuits. A variety of resistance-change technologies show promise in this respect, but a new approach that is based on switching in copper-doped silicon dioxide may be the simplest and least expensive to integrate. This paper describes the characteristics of W-(Cu/SiO2)-Cu programmable metallization cell (PMC) devices formed by the thermal diffusion of Cu into deposited SiO2. PMC devices operate by the electrochemical control of metallic pathways in solid electrolytes. Both unipolar and bipolar resistive switching could be attained in these devices. Bipolar switching, which is identical to that seen in PMC devices based on other solid electrolytes, was observed for low bias (a few tenths of volts) and programming currents in the microampere range. The resistance ratio between high and low states was on the order of 103, and a multibit storage is considered possible via the strong dependence of ON-state resistance on programming current. The low and high resistance states were stable for more than 5 x 104 s. The devices could be made to exhibit unipolar switching using a negative bias on the order of -1 V combined with erase currents of hundreds of microampere to a few milliampere. In this case, the OFF/ON ratio was 106.