Multigate Nanowire Research Articles

Design and Analysis of a Symmetrical Low-κ Source-Side Spacer Multi-gate Nanowire Device

Design and Analysis of a Symmetrical Low-κ Source-Side Spacer Multi-gate Nanowire Device

Performance Enhancement of GAA Multi-Gate Nanowire with Asymmetric Hetero-Dielectric Oxide

In this paper, a Multi-gate asymmetric hetero-dielectric oxide gate all around nanowire MOSFET device (MG-AHD–GAA-NW) is proposed for the low power standby, memory and sensor applications. The architecture of the proposed device is supported by segmented multiple gate with asymmetric hetero-dielectric oxide high-K(HfO2/TiO2) on the source side and SiO2 on drain side. Firstly, the effect of silicon thickness on conventional single gate cylindrical GAA MOSFET is studied. On reducing the thickness of silicon, a decrease in OFF current is observed. Further, to achieve best performance of the device at reduced silicon thickness(tSi = 5 nm) with quantum confinement effects, the proposed device is introduced. It is observed that at reduced silicon thickness (tSi = 5 nm), a low leakage current of 10−14A and ON current of 10−5A is obtained. The comparison of MG-AHD–GAA-NW with conventional single gate cylindrical GAA at tSi = 5 nm shows decrease in OFF current and increase in ON/OFF current ratio by 67.4% and 230% in MG-AHD–GAA-NW at same silicon thickness respectively. The proposed model is analysed by the various performance metrics such as transconductance(gm), and device efficiency(gm/ID).The proposed device exhibits lower DIBL of 16.7 mV/V, improved subthreshold slope of 62.28 mV/decade, higher ON/OFF current ratio of 8.87 × 108, higher transconductance and optimal threshold voltage. The effect of traps in semiconductor/gate oxide interface on device performance is also studied. Finally, to achieve the best performance of the device at circuit level implementation, the results of PMOS are matched with NMOS using work function engineering and thus V-shaped curve is obtained for both type of MOSFET followed by CMOS inverter as an application is also presented using the proposed device structure.

A Superconducting Binary Encoder with Multigate Nanowire Cryotrons.

Many classic and quantum devices need to operate at cryogenic temperatures, demanding advanced cryogenic digital electronics for processing the input and output signals on a chip to extend their scalability and performance. Here, we report a superconducting binary encoder with ultralow power dissipation and ultracompact size. We introduce a multigate superconducting nanowire cryotron (nTron) that functions as an 8-input OR gate within a footprint of approximately 0.5 μm2. Four cryotrons compose a 4-bit encoder that has a bias margin of 18.9%, an operation speed greater than 250 MHz, an average switching jitter of 75 ps, and a power dissipation of less than 1 μW. We apply this encoder to read out a superconducting-nanowire single-photon detector array whose pixel location is digitized into a 4-bit binary address. The small size of the nanowire combined with the low power dissipation makes nTrons promising for future monolithic integration.

Electron Transport in Multigate InxGa1–x As Nanowire FETs: From Diffusive to Ballistic Regimes at Room Temperature

The III-V semiconductors such as In x Ga 1-x As (x = 0.53-0.70) have attracted significant interest in the context of low power digital complementary metal-oxide-semiconductor (CMOS) technology due to their superior transport properties. However, top-down patterning of III-V semiconductor thin films into strongly confined quasi-one-dimensional (1D) nanowire geometries can potentially degrade the transport properties. To date, few reports exist regarding transport measurement in multigate nanowire structures. In this work, we report a novel methodology for characterizing electron transport in III-V multigate nanowire field effect transistors (NWFETs). We demonstrate multigate NWFETs integrated with probe electrodes in Hall Bridge geometry to enable four-point measurements of both longitudinal and transverse resistance. This allows for the first time accurate extraction of Hall mobility and its dependence on carrier concentration in III-V NWFETs. Furthermore, it is shown that by implementing parallel arrays of nanowires, it is possible to enhance the signal-to-noise ratio of the measurement, enabling more reliable measurement of Hall voltage (carrier concentration) and, hence, mobility. We characterize the mobility for various nanowire widths down to 40 nm and observe a monotonic reduction in mobility compared to planar devices. Despite this reduction, III-V NWFET mobility is shown to outperform state-of-the-art strained silicon NWFETs. Finally, we demonstrate evidence of room -temperature ballistic transport, a desirable property in the context of short channel transistors, in strongly confined III-V nanowire junctions using magneto-transport measurements in a nanoscale Hall-cross structure.

Method for Extracting Doping Concentration and Flat-Band Voltage in Junctionless Multigate MOSFETs Using 2-D Electrostatic Effects

In this letter, we propose a new method to extract the doping concentration and flat-band voltage in junctionless (JL) multigate nanowire (NW) mosfets. The method is based on using the gate-to-channel capacitance measurements of devices with different relatively small NW widths, for which 2-D electrostatic effects are appreciable, and plotting the average carrier concentration as a function of the gate voltage. The proposed method is verified using numerical simulations and experimental data for trigate JL transistors.