Multichip Power Module Research Articles

Adaptive Characterization Platform with Near Magnetic Field for Wideband Oscillations of Multi-Chip Power Modules

Adaptive Characterization Platform with Near Magnetic Field for Wideband Oscillations of Multi-Chip Power Modules

Fast and Accurate Parasitic Extraction in Multichip Power Module Design Automation Considering Eddy-Current Losses

Recent studies in power electronic design automation have introduced various models for parasitic extraction of multichip power module layouts. However, none of these studies consider the eddy current effect in the direct-bonded-copper substrate, accounting for 40-50% error in the extraction result. This work introduces a methodology for eddy-current consideration through numerical simulation and regression modeling. The regression model utilized in the characterization process in this work is fast and memory-efficient compared to the finite element approach. This characterization process can improve the accuracy of any partial element model without sacrificing performance. Combining this characterization process and partial element approach achieves less than 10% extraction error compared to Ansys Q3D while showing a maximum speed-up of 35× and 17× more memory efficiency. This method also significantly reduces the number of elements in the extracted netlist and the complexity of loop evaluation. This method is attractive for use with optimization routines and therefore has been used successfully in a layout optimization tool.

Paralleled multi-GaN MIS–HEMTs integrated cascode switch for power electronic applications

A cascode gallium nitride (GaN) switch integrating four paralleled GaN depletion-mode metal–insulator–semiconductor–high-electron-mobility transistors (MIS–HEMT) and a silicon MOSFET (Si-MOSFET) is presented. Each GaN chip is wire-bonded into a multi-chip power module to scale up the power rating. An optimized symmetric configuration and wire bonding of an integral package are used in the cascode switch. By utilizing an optimized packaging approach, the performance of the multi-GaN-chip cascode switch was evaluated through both static and dynamic characterizations. The constructed cascode switch provides a low-static on-state resistance of 72 mΩ and an off-state blocking capability of 400 V with a positive threshold voltage of 2 V. Analysis of dynamic switching characteristics are discussed and demonstrates stable dynamic on-state resistance (R DS-ON) in inductive load circuits with switching dependencies of voltage, frequency, time, and temperature. The extended defects from buffer caused a minimal decrease in dynamic and static R DS-ON with respect to hard switching conditions. However, there was no noticeable degradation in R DS-ON under harsh switching conditions. This study provides a complete analysis of the multi-GaN-chip cascode switch, including MIS–HEMT manufacturing, cascode packaging and static and dynamic characterizations.

PowerSynth 2: Physical Design Automation for High-Density 3-D Multichip Power Modules

Moving towards an electrified world requires ultra-high-density power converters. With the adoption of wide-bandgap semiconductors (e.g., SiC, GaN), the next-generation power converters are on the horizon. However, the complexity of compact and high-speed converters is beyond the current industry-standard design flow based on manual and iterative steps. Therefore, research on design automation and optimization has been identified as an emerging topic in the power electronics society. Among different components of the converter, the physical design of power modules has proven critical for achieving high power density and energy efficiency. We present the latest design automation flow for high-density (2D/2.5D/3D) and heterogeneous multi-chip power modules (MCPM) through PowerSynth 2 framework. In this work, we further demonstrate electro-thermal optimization for State-of-the-Art (SOTA) 3D packaging technologies. Using the latest PowerSynth 2 framework, electro-thermal design optimization is carried out on a sample 3D MCPM layout using both exhaustive and evolutionary search methods. The optimized design is hardware-validated against physical measurements. The measurement result has shown an order of magnitude productivity improvement within 10% accuracy compared to the SOTA industry design flow.

A Method to Derive the Coupling Thermal Resistances at Junction-to-Case Level in Multichip Power Modules

A method to derive the junction-to-case level coupling thermal resistances among paralleling chips in the multichip semiconductor power module has been proposed in this article. It is revealed that the traditional structure function methodology (SFM), which is developed for analyzing the self-heating effect of the driving-point chip, cannot be applied directly in the thermal coupling analysis, where the influence of the driving-point chip on the neighboring acceptor chip is concerned. This article shows that by combining the traditional SFM with the frequency-domain analysis (FDA), the effective separation points between the module case and the external cooling setup can be identified in both time and frequency domains, which correspond to the characteristic frequency points in the complex loci of the thermal impedance curves. By extracting the amplitudes at the characteristic frequencies from the complex loci in the FDA, the junction-to-case level coupling thermal resistances can be derived. Both simulation and experimental study have been carried out to verify the concept. The agreement between the two justifies the proposed method.

Layout-Dominated Dynamic Current Balancing Analysis of Multichip SiC Power Modules Based on Coupled Parasitic Network Model

Multichip silicon carbide (SiC) power modules with Kelvin-source connections are commonly used in applications requiring large capacity. As a result of the parasitic effect induced by the interconnections in module packaging, the dynamic current mismatch among paralleled dies limits the available capacity of power modules. This article presents a general analysis on the mechanism of layout-dominated dynamic current balancing in multichip SiC power modules, utilizing a coupled parasitic network model. Focusing on the interrelation of parasitic parameters in the power module, a coupled parasitic network model is developed specially for switching transients, and the dynamic current balancing equations are derived. For the multichip power modules with two different layouts, the parasitic parameters pertaining to the proposed model are extracted by the finite-element analysis (FEA). The acquired parasitic parameters considering magnetic coupling are utilized to calculate and verify the dynamic current balancing equations. Moreover, based on these parasitic parameters, the electromagnetic coupling simulation is performed to evaluate the dynamic current sharing. Furthermore, for the validation of the proposed model and equations, experiments are conducted with the fabricated power module prototypes.

Conventional and topologically optimized polymer manifolds for direct cooling of power electronics

Single-phase liquid-cooled heat sinks are a preferred mode of thermal management for many power dense electronic applications. This paper studies the design, optimization, and thermal-hydraulic performance of polymer manifolds directing coolant to the base plate of multi-chip power modules. Direct cooling eliminates the need for thermal interface materials which form a major bottleneck to junction-to-coolant thermal resistance reduction in state-of-the-art metallic cold plates. We use 2D topology optimization (TO) to develop designs using side view (SVTO) and top view (TVTO) sections of the flow domain in contact with the power module base plate. We also use 3D TO design (CTO) which combines SCTO and TVTO. The TO designs are compared against conventional mini-channel designs including rectangular, zig-zag and serpentine channels. Cooling performance of the different designs is computed using computational fluid dynamic (CFD) simulations. Experimental quantification is achieved through measurements of the silicon carbide device junction temperature and inter-device temperature difference along with the pressure drop influencing the pumping power requirement. The CFD simulations were used to identify optimized manifold designs which were fabricated using selective laser sintering of PA12 and validated experimentally using surrogate heaters. Zig-zag designs showed the best performance among the conventional designs (0.93 (cm2·K)/W), at the cost of high pressure drop (> 2.4 kPa). Serpentine channel designs were effective in limiting inter-device temperature difference (< 0.26⁰C) through multiple changes of flow direction. The TO designs improved the performance (1.1 (cm2·K)/W) when compared against conventional channels showing lower maximum temperatures with lower pressure drops (0.8 kPa). Fluid manifolds are shown to greatly influence the coolant flow field, leading to flow maldistribution with low velocity pockets, emphasizing the need for optimizing the complete manifold design.

Lumped Thermal Coupling Model of Multichip Power Module Enabling Case Temperature as Reference Node

Insulated gate bipolar transistor (IGBT) modules with multiple chips have wide range of applications, and the correct estimation for the thermal behaviors inside IGBT modules is becoming crucial. Thermal impedance matrix is one of the most adopted approaches to describe the thermal-coupling effect of IGBT module. For simplicity of analysis, the heatsink or ambient temperature is typically chosen as the reference node for the thermal-coupling impedance term, while the case temperature is simplified or ignored. This letter provides a thermal coupling model enabling case temperature as reference node. This proposed model decouples the thermal coupling impedances of IGBT module itself and external cooling condition, so that the modeling of cooling conditions outside device and inside the power module, can be separately considered. The characterization method and advantages of the proposed model are verified by an experimental demonstration, and the potential applications are further discussed.

A Technique for the In-Situ Experimental Extraction of the Thermal Impedance of Power Devices

In this letter, an innovative technique is presented, which allows the experimental extraction of the junction-to-ambient thermal impedance (Z_TH) of power devices operating in their application environment (<i>in situ</i>). The technique draws inspiration from the thermal characterization of RF transistors, and is based on simple measurements of electrical signals, while not requiring a thermochuck/cold-plate, the calibration of a thermometer, as well as temperature sensors or IR cameras. The validation of the technique is unambiguously performed by applying the simulated experiments strategy on a SiC-based multi-chip power module.

Graph-Model-Based Generative Layout Optimization for Heterogeneous SiC Multichip Power Modules With Reduced and Balanced Parasitic Inductance

Multichip silicon carbide power modules with integrated snubbers are promising for large-capacity converters with high speed and cost efficiency. In the design stage, the parasitic inductance of module layout generally attracts the primary efforts of designers because of its severe impact on dynamic performance, e.g., voltage overshoot and transient current imbalance. However, due to the complexity of the heterogeneous layout, the solution space and development efficiency are always limited by the traditional manual design approach. Thus, this article proposes a generative method to optimize the layout autonomously. First, a graph model is built to describe heterogeneous layouts with all interconnectivity and design constraints retained. Based on the model, integer programming is introduced to generate layout templates with variable geometric topologies. Then, coupled with a self-developed discrete extractor, the Pareto-front is obtained by genetic algorithm, providing a tradeoff boundary for loop inductance and branch mismatch. The proposed method is systematic, flexible, and requires few designers’ expertise. A 1200 V/240 A half-bridge module is designed and fabricated to validate its capability. The experimental results show that the loop inductance of 5.59 nH is achieved, and less than 5% of the transient current imbalance is realized under 6.2 A/ns turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> in the rated.

Circuit-Based Electrothermal Modeling of SiC Power Modules With Nonlinear Thermal Models

Silicon carbide (SiC) power devices have the potential to operate at high temperatures beyond the capabilities of silicon power devices. At increased temperatures, the temperature-dependent material properties of the SiC die and the package multilayer structure can influence the electrothermal (ET) device performance. In this article, a new step-back-correction technique implemented in a finite-difference-method-based thermal modeling tool is proposed to reduce the computational cost while maintaining a good accuracy of ET simulations for multichip power modules. The simulations take the temperature dependence of the thermal conductivity <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$k(T)$</tex-math></inline-formula> and both conduction and switching losses into account. The importance of considering <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$k(T)$</tex-math></inline-formula> for the accurate temperature prediction of SiC power devices is demonstrated for thermal impedance evaluations characterized by high-temperature swings, as well as for a 100-kHz boost converter with low device temperature amplitudes in the steady state. The proposed ET modeling is validated by COMSOL simulations and infrared camera measurements on an example of a custom-designed and custom-manufactured half-bridge SiC power module.

Design of an Integrated Power Module for Silicon Carbide MOSFET with Self-Compensation of the Magnetic Field

Compactness, efficiency, and light weight are the key topics in the design of power conversion systems for transportation applications. This demand is achievable by using wide band gap devices such as SiC devices, characterized by the high switching speed and low on-resistance. However, this trend imposes new challenges and the effect of parasitic elements of power package during switching transient becomes significant. Hence, new packaging solutions should be investigated for addressing this concern. This paper presents a new multichip power module architecture, where its design considering capacitive and inductive stray elements is carried out. Using Ansys Q3D Extractor, electromagnetic simulations are achieved to extract the inductive and capacitive parasitic element of one leg of a three-phase inverter.

Layout-Dominated Dynamic Imbalanced Current Analysis and Its Suppression Strategy of Parallel SiC MOSFETs

The multichip power module is a popular application for large-capacity and high-frequency converters. However, the existence of an asymmetric circuit layout has a significant influence on the current sharing among parallel SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). In this paper, the mechanism of the dynamic current imbalance resulting from the asymmetry of signal terminal confluence points (STCPs) is comprehensively investigated by theoretical analyses and simulation validations. It is demonstrated that the infinite norm of the common branch impedance coupling matrix (INC) can be used to characterize the dynamic current sharing performance. With an increase in the infinite norm, the dynamic current imbalance of parallel SiC MOSFETs gradually increases. Moreover, some significant discoveries are obtained. It is concluded that dynamic current imbalance is dominated by the asymmetry of the power source confluence point (PSCP). However, the asymmetry of the drain, gate, and auxiliary source confluence points does not exhibit a great effect on dynamic current sharing. Then, a novel circuit layout with an elliptical structure is proposed to suppress the dynamic current imbalance. Finally, some experimental tests are derived to validate the effectiveness of the designed layout. Compared with the commercial power module, experimental results show that the maximum dynamic imbalanced current with the proposed layout is reduced from 7.39 A to 1.37 A, and the largest dynamic current imbalanced deviation decreases from 28.66% to 5.11%.

Thermal Decouple Design of Multichip SiC Power Module With Thermal Anisotropic Graphite

Thermal design of power modules is necessary to miniaturize and ensure reliable operation of a high-density power conversion system. Miniaturization of the power module reduces the heat conduction area and increases thermal interference among the chips in the power module package. They increase the thermal resistance from the junction of the chips to the heatsink. This article designs a multichip power module with low thermal resistance using a high thermal conductive and anisotropic material graphite. The power module substrate that uses graphite as a heat spreader for a multichip power module is designed based on numerical simulation using the finite-element method to reduce the thermal resistance and thermal interference effect of the power devices on the power module substrate. The characteristics of the designed power module substrate are experimentally validated. The developed graphite power module reduces thermal interference by using its thermal anisotropy and achieves at least 8% lower thermal resistance than the conventional copper power module.

PowerSynth Design Automation Flow for Hierarchical and Heterogeneous 2.5-D Multichip Power Modules

As a critical energy-conversion system component, power semiconductor modules and their layout optimization has been identified as a crucial step in achieving the maximum performance and density for wide bandgap technologies (i.e., GaN and SiC). New packaging technologies are also introduced to produce reliable and efficient multichip power module (MCPM) designs to push the current limits. The complexity of the MCPM layout is surpassing the capability of a manual, iterative design process to produce an optimum design with agile development requirements. An electronic design automation tool called PowerSynth has been introduced with on-going research toward enhanced capabilities to speed up the optimized MCPM layout design process. As a part of this continuing research, in PowerSynth v1.9, a constraint-aware layout engine has been developed, which enables integrating heterogeneous components, handling complex geometry, exploring a larger solution space, improved success rate, and providing options for multiobjective optimization algorithms. The layout engine is generic, scalable, and efficient in performing electro-thermal optimizations on both 2-D and 2.5-D power modules. To validate these enhanced design capabilities, a 2.5-D full-bridge power module layout is designed, optimized, fabricated, and tested with measurement results matching closely with model prediction. This result closes the loop in the power electronics design process with an experimentally validated module design automation flow.

Heat-Flux-Based Condition Monitoring of Multichip Power Modules Using a Two-Stage Neural Network

Power semiconductor chips are paralleled in modules to increase current rating. Under thermo-mechanical stresses in service, the die-attach solder layers will gradually develop into different levels of degradation. Early fault detection requires to monitor the occurrence of such an uneven degradation pattern. Internal temperature differences only slightly affect the current sharing between chips, and some temperature sensitive electric parameters are considerably weakened at module terminals. This article presents an external heat-flux-based condition monitoring method, implemented in a two-stage neural network. The first stage consists of a set of subnetworks to represent the mapping between the electrical operating point of the module and its external temperature distribution, for a range of solder degradation patterns and severities. The respective levels of matching are then extracted and applied to the second stage to diagnose the health condition of the power module. This condition monitoring method, validated by experiment, can sensitively detect individual solder degradation in multichip power modules or multimodule power electronic systems.

DM Interference Propagation Mathematical Modeling in SiC Wirebond Multichip Power Module

In this brief, a novel differential-mode (DM) interference propagation mathematical modeling method based on parasitic inductive coupling theory for SiC wirebond multichip power module (SWMPM) with adjacent decoupling capacitor is proposed. Based on the proposed model, the strong and weak inductive coupling theory of DM interference equivalent circuit is proposed. And the influence of different position of decoupling capacitors on DM equivalent current is mathematically analyzed. A custom-made 1.2kV 160A power module based on DM interference optimized layout is built. It is compared with a commercial SiC power module, which can verify the feasibility and validity of the theoretical analysis.

Impact of stray-inductance imbalance on short-circuit capability of multi-chip SiC power modules

This paper discusses whether short-circuit capability of multi-chip SiC-MOSFET power modules is affected by stray-inductance imbalance between the chips or not. Experimental power modules equipped with commercial 1.2-kV, 19-A SiC-MOSFET chips are designed and fabricated in three different internal layouts, and then short-circuit capability of the power modules is measured. The experimental results show that the significant effect of stray-inductance imbalance can be seen only for 20 ns after the short-circuit event start. As a result, this paper reveals that multi-chip power module design doesn't need to pay attention to imbalance of stray inductance from the perspective of the short-circuit robustness.

Parasitic Inductance Modeling and Reduction for Wire-Bonded Half-Bridge SiC Multichip Power Modules

This article first developed an inductance model that includes the parasitic mutual inductance between parallel current path segments for SiC multichip power modules. Based on the developed model, the SiC multichip module's transient response was analyzed, important parasitic inductances were identified. The layout was improved based on the transient analysis. The improved package layout can reduce the parasitic inductance without increasing the fabrication difficulty. Experiments were conducted to validate the reduction of parasitic inductances. The parasitic ringing and the crosstalk effect were significantly reduced with the proposed technique. The thermal performance was also improved with the proposed layout.

Numerical Simulation and Analytical Modeling of the Thermal Behavior of Single- and Double-Sided Cooled Power Modules

This article presents the detailed thermal analysis and modeling of multichip power modules (PMs). For the first time, a fair thermal comparison between the widespread single-sided cooled (SSC) technology and the innovative double-sided cooled (DSC) one is presented. The latter solution emerges among all packaging techniques due to its improved electrical performances and mechanical reliability. The investigation is carried out using 3-D finite-element method thermal simulations automated by an in-house routine. The PMs under test are thoroughly studied in a wide range of boundary conditions (BCs) in order to support the choice of an appropriate cooling strategy and the comprehension of the heat spreading (HS) effect occurring in such domains. In addition, attention is paid to dynamic behavior. Thermal modeling strategies are then proposed and discussed. As the main finding, no relevant thermal discrepancies were observed in the two PM technologies. In most of the BCs, the SSC PM enjoys an enhanced HS effect leading to a better thermal behavior with respect to the DSC counterpart, the adoption of which is justified only in the presence of excellent cooling systems.