Abstract
Recent studies in power electronic design automation have introduced various models for parasitic extraction of multichip power module layouts. However, none of these studies consider the eddy current effect in the direct-bonded-copper substrate, accounting for 40-50% error in the extraction result. This work introduces a methodology for eddy-current consideration through numerical simulation and regression modeling. The regression model utilized in the characterization process in this work is fast and memory-efficient compared to the finite element approach. This characterization process can improve the accuracy of any partial element model without sacrificing performance. Combining this characterization process and partial element approach achieves less than 10% extraction error compared to Ansys Q3D while showing a maximum speed-up of 35× and 17× more memory efficiency. This method also significantly reduces the number of elements in the extracted netlist and the complexity of loop evaluation. This method is attractive for use with optimization routines and therefore has been used successfully in a layout optimization tool.
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