Multichip Module Technology Research Articles

特集 ＭＣＭ技術 ２ 応用 システム・オン・チップ化に向けてのＭＣＭ技術の応用

特集 ＭＣＭ技術 ２ 応用 システム・オン・チップ化に向けてのＭＣＭ技術の応用

Relationship of crystallographic orientation and impurities to stress, resistivity, and morphology for sputtered copper films

Copper has 44% higher conductivity than aluminum, making copper an attractive interconnect metal for advanced multilevel interconnections in integrated circuits (IC) and multichip modules (MCM). Since sputter deposition is widely used in IC and MCM fabrication, the properties of sputtered copper films are investigated in this study. In particular, MCM technology requires relatively thick coatings (5–8 μm), which can result in high stress. Thin film stress can lead to dielectric cracking, wafer bow, and reduced operating lifetime. This study reports the residual stress, morphology, and electrical resistivity of annealed copper coatings as a function of the thin film crystal orientation determined by x-ray diffraction. We found that the stress and electrical resistivity of copper thin films can be significantly reduced by controlling the orientation of the copper crystallites.

Overlay high-density interconnect: a chips-first multichip module technology

A high-density interconnection (HDI) technology that involves placing bare chips into cavities on a base substrate and fabricating the thin-film interconnect structure on top of the components is described. The interconnects to the chip I/O pads are formed as part of the thin-film fabrication process, thus eliminating the need for wire bonds, tape-automated bonds (TABs), or solder bumps. The need for advanced packaging and interconnection and the standard chips-last multichip module (MCM) technologies are reviewed. The HDI chips-first MCM technology's IC pretest requirements and approaches, substrate and packaged parts test, and substrate packaging are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Excimer Laser Structuring of Epoxy Resin Layers for MCM‐L Applications

Multichip module packaging enables a significant increase of interconnect densities and performance of electronic systems. Multichip module technology based on laminate materials (MCM‐L) is attractive due to low cost and use of the standard equipment used by PCB manufacturers. The most limiting factor for higher wiring densities in PCB technology is the mechanical drilling of plated‐through holes. Using 0.3 mm drill diameters, 0.5 mm land diameters are required, which limit the area for routing of tracks. Therefore, alternative dielectric materials, which can be structured photolithograpically, by plasma etching or laser drilling, are very attractive for MCM‐L technology. In this paper an epoxy resin layer, commercially available as a solder mask, is investigated as an interdielectric layer. Via hole drilling is investigated using an excimer laser. To show process feasibility, a two‐layer wiring system is fabricated using the excimer laser structured epoxy resin as an interdielectric layer on conventional epoxy board (FR‐4).

Multichip modules (MCMs): a review of the status quo

Multichip modules (MCMs) are an advanced packaging technique that features greater packing density and performance than traditional packaging technologies. At present, the lack of a merchant MCM infrastructure and high costs are together limiting the widespread use of MCM technologies outside the captive markets. However, in the near future, current packaging technologies will not be able to deliver the equivalent size, weight and reliability advantages offered by MCM technology. Evidence shows that MCMs are migrating towards low- and mid-range computer applications thanks to technological advancements and to the increased demands for higher performance within this market. This paper presents MCM classifications, design issues, interconnection techniques, trends in the technology and the changing marketplace and applications for these packaging systems.

Optical interconnections within multichip modules

As very large scale integration technology advances toward higher complexity and density, future generation computing and communications systems will operate at speeds of several hundred megahertz or even gigahertz. In many cases, the capability of the interconnections within these systems to support the required speeds and densities will be a formidable challenge. Multichip-module (MCM) technology is one approach to overcome some of the interconnection bottlenecks, but even such an advanced packaging system has limitations, especially for very high speed complex systems. Optical interconnections offer the potential for improved performance in terms of large bandwidth, noise and crosstalk immunity, lower power dissipation, and large fan-out capability. We discuss the use of optical interconnections within multichip modules. We consider three specific applications-input/output access to the MCM, global signal distribution, and chip-to-chip interconnects-and discuss both free-space and guided-wave implementations of optical interconnects.

Cost saving opportunities with multichip modules

Multichip modules (MCMs) have been utilized in the electronics industry, predominantly for physical size and performance driven applications. An MCM application that was driven by cost is described. The study of MCM technologies focused on the MCM assembly and interconnect to the motherboard. Models were developed to calculate the assembly and test costs for MCMs using wirebond and TAB technologies. Another model was used to evaluate interconnect options, both separable and nonseparable (e.g. soldered). A cost analysis verified that a significant cost savings was achieved by using MCM technology and, along with a technical evaluation of the alternatives, led to an MCM physical design for this application.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Can anyone in the US rescue MCMs?

MCM technology in the US is in a difficult stalemate these days. Most developers are sitting on quality prototypes a top declining budgets. Some, like IBM, DEC and AT&T, even have the capability to manufacture a few hundred thousand units. But without solid orders for cost-effective volumes, nobody's moving beyond the prototypes or pilot production stage. We've all been in that movie! The handful of small companies which originated the market has basically gone by the wayside: Unistructure, APS/Raychem, and Mosaic Systems have closed altogether, Honeywell and Alcoa have switched from fab to just design, Rogers is being sold, and nChip is scurrying for more capital. The movie script never seems to change - only the actors.

Multichip Module Technology: The Transition from Research to Manufacture

The benefits of the thin film multichip module (MCM‐D) approach to high density packaging for VLSI devices have now been amply demonstrated by a number of research groups. The successful emergence of a viable multichip module industry from this research base will, however, depend upon the installation of an industry‐wide manufacturing infrastructure. This will have to provide the necessary range of concurrent design capabilities, make pretested bare die available, and include multichip module vendors who can offer an integrated capability in module design, substrate layout and manufacture, advanced module assembly, packaging and test. Each of these areas of MCM‐D technology merits detailed attention in its own right, sufficient to justify many individual papers and presentations. This present paper focuses on just one of these topics and addresses the approach taken by GEC Plessey Semiconductors (GPS) to the development and control of a highly manufacturable MCM‐D silicon substrate process. The GPS ‘Process I’ four‐layer metal, aluminium‐polyimide substrate technology is described, the technology development and process control test structures are detailed and process characterisation data presented.

High rate single substrate polymer etching for multi- chip-modules (MCM) and off-chip-interconnect applications

The paper reports on work performed on MCM technology using polyimide as dielectric material which is being patterned by means of a dry etching technique. The main requirements for the patterning step are high rate and steep profiles. This can be achieved using low frequency plasma generation (25 kHz) which results in a fast and highly anisotropic etch with good selectivities towards the masking material. Chromium, copper and spin-on-glass have been looked at as masking materials. Results obtained show aspect ratios greater than 20:1 and clean surfaces making the technique suited for MCM's.

Ultra-Dense: an MCM-based 3-D digital signal processor

The DSP3 Multiprocessor Project has produced a multi-GFLOP machine that is applicable to a variety of signal processing and pattern recognition problems. A companion program, the Ultra-Dense Project, is utilizing silicon-on-silicon multichip module (MCM) technology and innovative advanced packaging and physical design to achieve a parallel three-dimensional digital signal processor based on the DSP3. The authors present an overview and outline systems architecture the micro-interconnect technology (Si-on-Si MCM), and advances in physical design and packaging technology leading to an ultra-dense project demonstration. >

Crisis in technology: the questionable US ability to manufacture thin-film multichip modules

It is argued that even though the technology choices are available, the ability to procure deposited multichip modules (MCM-D) in the US is seriously threatened by the inability to obtain volume orders. The result is the withdrawal of capital at just the time when the capabilities are more and more certain. The future capability in the necessary thin-film multichip module technology may not exist if the companies with capability fold before volume orders are placed. A prescription to stimulate volume production of thin-film MCMs is offered.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Stresses in Thin Film Multilayer Interconnect Structures

AbstractThe difference in coefficient of thermal expansion (CTE) between substrate, polymer, and metal leads to complicated stress fields in multilevel interconnect structures that can potentially compromise reliability. This study uses a materials set representative of the General Electric High Density Interconnect (HDI) multichip module technology to monitor the stress level in the thin film layers of metal and polymer. A Kapton HN® film is bonded to a substrate with heat and pressure using a thin layer of Ultem 1000® thermoplastic as an adhesive. Mechanical test structures consist of single or multilayer thin films fabricated on oxidized silicon or alumina substrates. Layers consist of Ultem, Ultem/Kapton, metal (Ti/Cu/Ti), and Ultem/Kapton/metal. The composite stress due to fabrication and thermal cycling between ambient and 275°C is determined by substrate deflection. The initial stress in the polymer materials is due to the thermal excursion during fabrication. Initial metal stress is intrinsic but becomes extrinsic upon thermal cycling. The composite stress in multilayer structures shows a contribution from each individual layer. The relatively low processing temperature minimizes the magnitude of the stress.

Multichip packaging-a tutorial

Several aspects of the multichip module technology, including its functions, leverages, applications, and markets, are reviewed. All the packaging technologies used in multichip, such as sealing and encapsulation, heat removal, chip level connections, thin film, ceramic, and printed wiring, are discussed. The module corrections and electrical testing used in forming a high-performance or portable system are also discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

High-yield assembly of multichip modules through known-good IC's and effective test strategies

Multichip module technology has been shown to offer significant improvements for electronics equipment in the areas of miniaturized size, reduced weight, capability for higher frequency operation, improved thermal performance, and improved reliability. Production applications for multichip modules (MCMs) have grown from high-end computer and aerospace modules to include such diverse products as telecommunications, automotive, and consumer electronics modules. One of the keys to economic success in all applications is the achievement of high manufacturing yields. Yield losses must be kept very low compared with module costs in order to remain economically competitive. Two parameters with a very strong impact on manufacturing yield, known-good components entering assembly and test strategies at various levels of assembly, are discussed. Current industry practice is surveyed and recent progress on MCM infrastructure development is summarized. >

SI-ON-SI MCM TECHNOLOGY AND ITS APPLICATIONS

Multichip Module (MCM) packaging has been used in high-end systems, such as mainframe and supercomputers for some time. Rapid advances in VLSI technology and novel system architecture concepts have presented both challenges and opportunities for MCM technologists. We should not just try to find a solution, but also try to take a long-term view and plan the technological development. We would like to develop MCM technology which has a broad range of applications from consumer products to supercomputers. The technology should focus on low cost, high performance, compact size, and high reliability. We believe that it is most attractive to leverage IC technology and surface mount technology (SMT). Therefore we select Si wafer as the substrate, Al as the metallization, polyimide as the dielectrics, Ta-Si as the resistor material, and Si oxide and nitride as the dielectrics for capacitor. Flip-chip solder attachment are used to assemble chips on the substrate. We view our version of MCM as a “giant chip” rather than a miniaturized printed wiring board. This “giant chip” contains mixed device technologies which cannot be obtained by current device technology. The migration path should be from small to large module. The infrastructure of the CAD system and the testing system is critical for the development of MCM technology. Potential applications and implementations of MCM technology are given in this paper.

Physical design issues for very large ATM switching systems

The authors examine the physical design issues associated with terabit/second switching systems, particularly with regard to the customer access portion of the switch. They determine the physical design requirements in the areas of backplane interconnections, integrated circuit packaging, and circuit board technology and identify areas where existing- or near-future physical design technologies are inadequate to meet the requirements of this application. A new 3D interconnection architecture that solves some of the problems encountered at the backplane level is suggested. It is also suggested that multichip module technology will help meet some of the speed and density requirements at the chip packaging level. Some of the system-level consequences of the proposed model are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Polystrate and Ultrastrate: Complementary Multichip Module Technologies

CMOS devices are approaching the 50 MHz threshold at which conventional electronic assemblies—based on packaged components (SMD, PGA, etc.) mounted on high‐density printed circuit boards—impose a serious penalty on the speed of the raw die provided by the semiconductor vendors. To improve the packaging density and to reduce the resistive and capacitive loads as well as signal delays at the second level of interconnection, new packaging concepts for VLSI and ULSI components are imperative. Multichip modules (MCM) seem to be the only adequate solution to the interconnect problem. Ultrastrate—the author's company's MCM technology with multilayer thin‐film build‐ups—is briefly presented. Life cycles for products in the electronics industry are becoming ever shorter. Electronics engineers must package more complicated circuits in smaller volumes and in a shorter time. On the other hand, prototyping an MCM from the electrical schematic takes at least 12 weeks. There is as yet no equivalent of a PCB breadboard for MCMs! In response to this situation, Polystrate is a new process which has been developed to provide a flexible and fast prototyping tool for MCMs. It satisfies the most stringent requirements with regard to performance, economics and ease of modification, and offers a very fast turn‐around time. The technological synergies between Ultrastrate and Polystrate allow for a smooth transition between the prototyping and production phases.

Multi‐chip Modules for Telecom Applications

System performance can be improved by the use of MCM (multi‐chip module) technology. Better signal transmission properties, lower power dissipation if C‐MOS chips are used and decreased physical volume will be obtained. Today MCM is an expensive technique, but the authors' cost analysis shows that it has the potential to become more cost‐effective than the standard technique of using single chip packages. It can also become more cost‐effective to use the MCM technique than to increase the number of gates on the silicon chip over a certain level. In order to study the properties of MCM technology, a project has been started at the authors' company in which a processor application is built up on three different types of MCM substrates.

Current capabilities/needs and future possibilities of multichip modules (MCM's)

The state of the art was discussed in terms of costs, densities, speeds, sizes, yields, rework, testing methodologies, and thermal capabilities for the principle production interconnects. Comparisons were made for each of the newer MCM (multichip module) technologies for which data are available. Observations about costs, reworkability, assembly methods, yields, and testing were made to indicate the author's views on where and how costs for MCMs can be driven down to become competitive with existing interconnect systems.