Abstract
The authors examine the physical design issues associated with terabit/second switching systems, particularly with regard to the customer access portion of the switch. They determine the physical design requirements in the areas of backplane interconnections, integrated circuit packaging, and circuit board technology and identify areas where existing- or near-future physical design technologies are inadequate to meet the requirements of this application. A new 3D interconnection architecture that solves some of the problems encountered at the backplane level is suggested. It is also suggested that multichip module technology will help meet some of the speed and density requirements at the chip packaging level. Some of the system-level consequences of the proposed model are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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