An Implementation of Integral Low Power Techniques for Modern Cell-Based VLSI Designs

Abstract

Recent research has proposed several low-power design techniques for VLSI circuitry in nano-scale CMOS era. However, these techniques always involve custom layout design or novel Electronic Design Automation (EDA) flows. In this paper essential low power techniques such as voltage separation, body bias and power switch are implemented in existent place and route (P&R) tools. These techniques enable the possibility to integrated low power techniques into standard Cell-Based physical design flow. The result of these research shows a little overhead in design procedure equally area overhead compare with fully custom design flow. The proposed low power design techniques can be cooperated with modern power management system to enable the power reduction in targeting circuitry with small implementation overheads. disconnect power supply of functional block. This is achieved by connecting a transistor in series with the power supply of the block (3). In practice, a network of power switch may be necessary to efficiently control and reduce leakage power. Another dynamic technique, body bias, needs dynamically changing the body bias applied to the block (4). During active mode, forward body bias (FBB) is applied to increase the operating frequency. Alternately, reverse body bias (RBB) can be applied during idle mode for further leakage savings. This body bias technique can be combined with a power switch to provide even further leakage power savings. However, the majority of low power design circuits are implemented with Fully-Custom design. In order to automate design phase and satisfy the demand of Time-To-Market requirement, integrating low power techniques into Cell- Based physical design flow is essential. In order to apply the benefits offered by low leakage techniques into Cell-Based design, some physical design issues must take into considerations. Therefore, the general physical design flow must be modified for the integrating low power techniques into physical design. In this paper, a low power physical design methodology is presented. By using this low power design methodology, a Cell-Based design circuit with low power techniques features is available. Our goal is to create a regular physical design flow utilizing existent EDA tool.