Multichip Module Applications Research Articles

Study on the properties of conductive adhesives in various curing manners for MCM applications

In this work, the properties of solvent and solvent-free electrically conductive adhesives (ECAs) in four curing manners and after solder reflows are investigated for multi-chip module applications. The curing behaviors and thermal degradation of solvent and solvent-free ECAs are also studied by differential scanning calorimeter and thermogravimetric analysis, respectively. The bulk resistivity of ECAs in four curing manners is significantly different, even if they are cured at the same temperature and time. The conductive trends of solvent and solvent-free ECAs are also different. The good and poor conductive properties of solvent ECA are obtained at curing temperature starting from room temperature and setting temperature, respectively. However, the results of solvent-free ECA are opposite. All the bulk resistivity and the coefficients of thermal expansion of solvent and solvent-free ECAs tend to decrease after solder reflows. The reasons are studied by thermomechanical analyzer, thermogravimetric analysis, topography and deformation measurement, and scanning electron microscopy.

OM4 bend insensitive multi-mode fibers’ usefulness for MCM integration

► The influence of high temperature exposure on OM4 fibers’ mechanical properties. ► Researching OM4 class fibers for use in innovative Optical Multi Chip Module. ► The influence of bending at a very small radius, up to 2 mm, on MM fibers. For future generations of electronic systems, a severe bottleneck is expected on the interconnection level and the use of optical interconnection is considered as one of the most promising solutions in this matter. Recent progress in fiber development resulted in new generation of optical fibers that are bend insensitive. This makes them ideal for Multi Chip Module (MCM) application. This paper focuses on OM4 bend insensitive multi-mode fibers’ usefulness for MCM integration, particularly the investigation of MM fiber loss is presented, which is influenced by bend diameter and the fiber's mechanical performance under influence of high temperature (400 °C–1000 °C adequate to MCM production process).

Dielectric thickness and ground width effect on multilayer coplanar components and circuits for ceramic multichip modules

AbstractThis article investigates the effect of dielectric thickness and ground width on the performance of multilayer conductor backed coplanar waveguide lumped elements and circuits fabricated on advanced multilayer photoimageable thick‐film ceramic multichip module (MCM) technology. From the S‐parameters, the effective dielectric constant is extracted to investigate the effect of dielectric thickness and ground‐width on transmission line dispersion. The equivalent circuit parameters for multilayer ceramic‐based capacitors and inductors are investigated for various dielectric thicknesses and ground‐plane widths. Finally, the practical effect of dielectric thickness and ground width are investigated for a highly compact and high performance lumped element low pass filter at 3 GHz, developed for cost‐effective MCM applications. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:1127–1132, 2012

An optimized QFP structure for use in radio frequency multi-chip module applications

An optimized QFP structure for use in radio frequency multi-chip module applications

Commercial-off-the-Shelf (COTS) 3D Integration using Low Temperature Wafer Bonding

This paper reports on a successful 3D integration (3DI) of multi-purpose signal processor (MSP) chips with memory chips using die-to-wafer (D2W) and wafer-to-wafer (W2W) bonding technologies. 3D integration enables compact systems of commercial-off-the-shelf (COTS) parts with high functionality using a wafer-level process for better thinning process uniformity and high yield throughput. The3D system is comprised of commercial Flash memory bare die and MSP bare die. The bare die are face-down aligned to a 150mm diameter silicon handle wafer with alignment marks polished silicon surface. Unique features on the commercial die are detected and used for die registration using a flip-chip bonder with vision automation. An adhesive film between the die and silicon handle wafer are used for temporary bonding. After the die-to-wafer population and bonding, the die substrates are thinned at the wafer-level to a target of 60 microns for the memory die and 25 microns for the MSP die, respectively. The thinned memory die set is permanently transferred onto a 150mm diameter silicon carrier wafer using a low temperature silicon covalent wafer bonding. Following bonding, an adhesive film release process is used to separate the memory die set from the temporary handle wafer. The thinned MSP die on a second handle wafer are then aligned to the thinned memory die set using a wafer-to-wafer alignment tool, and bonded with thin-film polyimide in a high-yield, low temperature wafer bonding process, followed by the release process to separate the MSP die set from the handle wafer. Finally, the MSP/memory stack are electrically connected using a via-last through-silicon-via (TSV) process. One of the key considerations for COTS 3DI is to meet the back-end-of-line (BEOL) thermal budgets of 350–400 Celsius. Plasma-assisted preparation facilitates the reduction in thermal budget for silicon covalent bonding and is performed at 150 Celsius, followed by a long-term annealing process at 175 Celsius. Stacking of thinned die relies on low temperature polyimide bonding that is performed at 200 Celsius. Fluorine and oxygen based plasma surface activation process and CTE-matched polyimide bonding play a critical role in enabling the low temperature bonding for this 3D MSP/memory integration. The thinning and bonding processing details that are presented in this paper are essential for COTS 3DI but can also be applied to several low-profile multi-chip module and packaging applications.

Analytical modelling of microstrip-like interconnections in presence of ground plane aperture

High-speed multichip module interconnects are characterised by planar transmission lines. An interconnect line with ground plane aperture is essentially a microstrip line with partially removed ground plane below the line. The authors report the closed-form analytical expressions for line capacitance and characteristic impedance of microstrip interconnect line with a ground plane aperture. The expressions have been obtained using variational analysis combined with transverse transmission line technique. The closed-form expressions are general and are obtained for a range of structure parameters and the dielectric constants. Results are compared with finite-difference time-domain simulations and measurements performed on a vector network analyser. The proposed study can find applications in the design of high-speed interconnects for printed circuit boards, radio frequency (RF) and multichip module applications. These are particularly useful where high impedance lines are required.

HF-contact elements for testing and multi chip module applications

In this paper a platform based on the composite IC concept (Semiconductor Industry Association in The NTRS, pp 63, 1994) will be presented that is optimized for high frequency applications. Key elements of the platform are coplanar waveguides and micro springs that are processed using MEMS technologies. Rotation symmetric micro springs with diameters between 500 and 125 μm with different widths and thicknesses were designed, simulated and fabricated. The best mechanical properties were obtained from springs with a diameter of 250 μm. They were made by electroplating of a nickel–tungsten-alloy. FEM simulation of the high frequency performance shows a good performance up to frequencies of 10 GHz.

Integrated Flip-Chip Flex-Circuit Packaging for Power Electronics Applications

A novel flip-chip flex-circuit packaging platform is described that enables integration of multiple power dies and control circuitry with an advantageous form factor. A key attribute of this packaging platform is to extend the well-established flex-circuit and flip-chip soldering technologies in signal electronics to power electronics applications. The planar interconnection and flip-chip method facilitate multilayer packaging structure with reduced packaging dimensions and reduced packaging parasitics. A half-bridge test vehicle designed and fabricated for DC/AC inverter applications (42 V, 16 A) with an overall flex-circuit module footprint less than 30% that of a discrete device printed circuit board implementation has been modeled and demonstrated experimentally. Electrical results, confirmed with circuit simulation incorporating parasitic inductance electromagnetic modeling, have shown a turn-off voltage overshoot reduction of over 40% and a switching energy loss reduction of 24% with the flip-chip flex-circuit implementation. The power flex platform has a strong potential for integrated multichip power module applications that require minimized packaging size and parasitic inductance for high switching frequency and efficiency.

Effect of Viscosity of Liquid Resin on Resin Self-Alignment Capability

We developed highly precise self-alignment process using resin materials for next generation microelectromechanical systems (MEMS), micro-opto-electro-mechanical systems (MOEMS) and optoelectronic multichip modules (OE-MCMs) applications. Although liquid resins have a characteristic as low as one tenth of the surface tension of solder in general, self-alignment capability could be achieved by using 3-D pads for positioning boundary. In this research, we propose the novel passive alignment mechanism in order to enhance understanding of alignment motion. Moreover, the influence of viscosity on alignment motion and alignment accuracy is demonstrated by scaled-up experiment. We could achieve highly precise alignment accuracy less than 0.4 μm.

Signal integrity and design consideration of an MCM for video graphic acceleration

This paper introduces a cost effective multichip module (MCM) for video graphic acceleration (VGA) of portable computers. A 1.7 million gate graphic processor IC and two 8 M byte DRAM chips have been integrated into a 31/spl times/31 mm/sup 2/ 4-layer PBGA. Signal integrity measurement and analysis has been performed to optimize performance of the present design and a direction for improvement for the next generation product. This study confirms that more consideration given to the MCM application at the IC design stage will maximize MCM performance.

A comparison of routing estimation methods for microelectronic modules

It is often necessary to estimate the number of board layers in electronic modules before detailed routing is possible. Several methods for estimating board interconnect requirements prior to the existence of a netlist have been developed. Some estimation approaches depend on the use of heuristics derived from studying actually routed designs, while others depend on geometric or statistical arguments. The applicability and uncertainties associated with these estimation techniques are not widely understood. In this paper several different routing estimation methods are applied to a variety of printed wiring board and multichip module applications. The accuracy with which the methods predict the amount of required wiring is compared.

Liquid cooling for a multichip module using Fluorinert liquid and paraffin slurry

The objective of the present study was to investigate the effect of phase change material on heat transfer enhancement in a multichip module application. The parameters studied in the present study include the mass fraction of paraffin slurry, the heat flux of simulated VLSI chips and channel Reynolds numbers. The size of paraffin slurry particles was within 10–40 μm. The local heat transfer coefficients for the paraffin slurry were larger than those for water. The paraffin slurry showed an effective cooling performance at high heat fluxes. The paraffin slurry with a mass fraction of 5% showed the most efficient cooling performance when the heat transfer and the pressure drop in the test section were considered simultaneously. The present experimental data at the fourth and sixth rows gave an excellent agreement with the values predicted by the Malina and Sparrow’s correlation, and a new empirical correlation for the water and paraffin slurry with a mass fraction of 5% was proposed at the first and sixth rows for a channel Reynolds number over 3000.

Study on the amorphous Ta 2O 5 thin film capacitors deposited by dc magnetron reactive sputtering for multichip module applications

Tantalum oxide (Ta 2O 5) thin film capacitors for multichip module (MCM) applications were investigated. Through the capacitor characterization and RBS compositional analysis, it was found that when the sputtering power and Ar flow rate is 200 W and 60 sccm, respectively, the stoichiometric Ta 2O 5 film can be obtained at the O 2 gas flow rate of 50 sccm. The low temperature annealing (150°C) is useful to increase the capacitor yield, but the annelaing in oxygen atmosphere causes the leakage current to increase. When the Ta-oxide capacitors were fabricated on the polymer-laminated substrate, leakage current increased and breakdown field strength decreased. These are due to the surface roughness effects of the polymer films and also the Al bottom electrode layer. It was demonstrated that the Ta 2O 5 capacitors fabricated on the Upilex-S polymer film can meet the requirements of integrated capacitors for MCM applications.

Thermal Placement Design for MCM Applications

This paper introduces an algorithm that focuses on the placement of the power dissipating chips for multichip module applications. The main design issue is addressed on the chip placement to achieve uniform thermal distribution. Our approach to the placement problem is based on the modified force-directed placement method. The proposed thermal force-directed placement method is to relate the force equations to the power dissipation values of the individual bare chip. Examples of multichip placement are presented. The finite element simulation results are also investigated and compared with quadrisection placement methods. [S1043-7398(00)01002-1]

Effect of planarization of the bottom superconducting yttrium-barium-copper-oxide layer in the multilayer structure

YBCO/YSZ/SiO/sub 2//YSZ/YBCO multilayer structures have been successfully grown on single crystal YSZ substrates. The YBCO superconducting layers (300 nm thick) were deposited using pulsed laser deposition (PLD). The YSZ layers (300 nm thick) which are biaxially aligned were deposited using PLD and ion beam assisted deposition (IBAD). A thick silicon dioxide layer (2-4 microns) was sandwiched between the YSZ layers to meet the low dielectric constant requirement for multichip module applications. However, if the bottom superconducting layer was patterned into interconnecting lines as required in device applications, the surface of the YSZ/SiO/sub 2//YSZ on top of the patterned bottom superconducting layer had a roughness of about 500 nm. As a result, the top YBCO was no longer superconducting. Thus, planarization of the patterned bottom superconducting layer becomes a key issue. We have developed a "fill-in and lift-off" process to fill the gap between the patterned bottom superconducting lines with YSZ, As a result, we were able to reduce the surface roughness of the bottom YBCO layer to about 10 nm so the top layer was superconducting with a critical temperature of 87 K.

Recent advances in plastic packaging of flip-chip and multichip modules (MCM) of microelectronics

The success in consumer electronics in the 1990's will be focused on low-cost and high performance electronics. Recent advances in polymeric materials (plastics) and integrated circuit (IC) encapsulants have made high-reliability very-large-scale integration (VLSI) plastic packaging a reality. High-performance polymeric materials possess excellent electrical and physical properties for IC protection. With their intrinsic low modulus and soft gel-like nature, silicone gels have become very effective encapsulants for larger, high input/output (I/O) (in excess of 10 000), wire-bonded and flip-chip VLSI chips. Furthermore, the recently developed silica-filled epoxies underfills, with the well controlled thermal coefficient of expansion (TCE), have enhanced the flip-chip and chip-on-board, direct chip attach (DCA) encapsulations. Recent studies indicate that adequate IC chip surface protection with high-performance silicone gels and epoxies plastic packages could replace conventional ceramic hermetic packages. This paper will review the IC technological trends, and IC encapsulation materials and processes. Special focus will be placed on the high-performance silicone and epoxy underfills, their chemistries and use as VLSI device encapsulants for single and multichip module applications.

Post-deposition processing of low temperature PECVD silicon dioxide films for enhanced stress stability

High rate plasma-enhanced chemical vapor deposited (PECVD) silicon dioxide films are attractive for multichip module (MCM) applications, but the incorporation of various hydrogen-related impurities in these films and the resulting stress instabilities make their properties less than desirable. Annealing of such films was performed in different ambients at temperatures significantly below the oxide densification temperature. The changes in the bonding nature and stress of these films, as a result of annealing, and during aging were studied. A considerable shift in the Si–O characteristic peaks and a decrease in the full width at half maxima (FWHM) of the Si–O stretching peak were observed for films annealed in nitrogen or a steam-nitrogen ambient at atmospheric pressure. During subsequent aging, these films showed negligible change in these parameters indicating their stability. Whereas, the films which were annealed in the chamber following deposition without breaking vacuum did not exhibit any appreciable change in Si–O peak position and FWHM during annealing but a very large change in these parameters during subsequent aging indicating their worst stability. Similar results were obtained from a stress stability study on these films. The results of this study suggest that moisture, which diffuses into the film during aging and/or annealing reacts with strained Si–O bonds and forms silanol (Si–OH). During annealing, the silanol reacts to reconstruct Si–O bonds and releases water as a by-product, thus the reason for the improvement in film quality is that the strain of the newly-formed Si–O bonds is much less than the strain of the original Si–O bonds.

Nanosecond pulsed excimer laser machining of chemical vapour deposited diamond and highly oriented pyrolytic graphite: Part I An experimental investigation

A laser beam offers the benefits of high precision, contamination-free, high speed, and low bulk temperature for machining of chemically vapour deposited (CVD) diamond thin films that in turn enable ultrafine finishing of diamond coated cutting tool inserts and drills, and for finishing and drilling of diamond coated multichip module applications. In this work, laser hole drilling and polishing of CVD diamond (free-standing diamond and coated tool inserts) and HOPG (highly oriented pyrolytic graphite) using a 248 nm wavelength, 23 ns pulsed excimer laser were conducted. The threshold energy fluence required for ablation of diamond and graphite was nearly the same but the material removal rate rapidly increases with the energy fluence for the graphite compared to diamond. At an energy fluence of 10 J cm-2, the depth removed per pulse was 0.05 μm and 0.30 μm for diamond and graphite respectively. Raman microprobe analysis indicates that the laser machining induced the transformation of diamond to disordered forms of carbon in CVD diamond and some transformation of graphite to diamond in HOPG. The experimental data indicates that the transformation of diamond to graphite requires an energy input of 1.44 × 107 J per mole. For a given set of laser parameters, the depth per pulse was substantially higher for diamond coated tool inserts compared to the free-standing diamond. The surface roughness of CVD diamond was reduced by 0.25 μm per pulse at an energy fluence of 16 J cm-2

An Innovation in Thermoplastic, Reworkable Adhesive Pastes

Today’s emerging markets in the electronic packaging industry require some unique properties in adhesives, especially in die attach applications. In multichip module (MCM) applications, for example, the low temperature reworkability of die bonds is of primary importance, particularly if known good die (KGD) are not employed. If KGD are used in the MCM, a temporary, reworkable die adhesive is also desirable for a KGD testing programme. Large area die on organic substrates, which are key to the more portable, high power computers, require a very compliant adhesive to absorb the high mismatch in expansions. An overview of the present adhesive technologies reveals some serious limitations in their application and performance. Traditional Ag epoxies, primarily because of their irreversible ‘thermosetting’ during cure, do not fulfill all the material requirements. Thermoplastic chemistries are ideal candidates for MCMs because of their reversible melting and resolidification properties. This paper details the development of a novel silver loaded thermoplastic paste that overcomes most of the deficiencies seen in present day adhesives. One of the main obstacles that has hindered the use of thermoplastic pastes as an adhesive has been the slow solvent extraction during the curing step. With current technology, this inherently slow solvent extraction typically requires a complex process of first depositing a flat profile, then removing the solvent with a pre‐drying step, and finally attaching the die by a heat/pressure step. A blend of components, hereafter referred to as DM4030, has been tested and compared against conventional materials in the industry. Functional properties of adhesion, resistivity, wire bonding and others are summarised for various temperature profiles. Long‐term reliability test results are shown for temperature cycling, temperature/humidity (85° C, 85% RH), and high temperature storage. For reworkability applications, die removal force as a function of temperature is also presented.

Characterization of High Rate Deposited PECVD Silicon Dioxide Films for MCM Applications

Silicon dioxide has recently received considerable attention as an interlayer dielectric for use in multichip modules (MCMs) because of its excellent properties. A high deposition rate at relatively low temperatures is desirable for process compatibility and high throughput. PECVD silicon dioxide films up to 7 μm thick were deposited at 1000 Å/min in a showerhead type system using , , and . Substrate temperature was varied from 250–350°C. The deposited films were annealed at various temperatures (up to 500°C). Uniformity, etch rate, film stress, refractive index, Si 2p and O 1s binding energies, and Si‐H and OH bonding configurations were studied. C‐V and I‐V characterizations of the films were performed to investigate their electrical quality. All the as‐deposited films exhibited moderate compressive stress. A considerable change in stress was observed after annealing the films in the above noted temperature range. OH content in the films was found to decrease and the hydrogen content in the films was found to increase with increasing deposition temperature. A good correlation between silanol (Si‐OH) and hydrogen content and silicon richness of the films with film stress was observed. The refractive index was found to decrease with increasing anneal temperature for all the films. Etching rates were lower for films deposited at higher temperatures. All films exhibited excellent breakdown characteristics.