Abstract

YBCO/YSZ/SiO/sub 2//YSZ/YBCO multilayer structures have been successfully grown on single crystal YSZ substrates. The YBCO superconducting layers (300 nm thick) were deposited using pulsed laser deposition (PLD). The YSZ layers (300 nm thick) which are biaxially aligned were deposited using PLD and ion beam assisted deposition (IBAD). A thick silicon dioxide layer (2-4 microns) was sandwiched between the YSZ layers to meet the low dielectric constant requirement for multichip module applications. However, if the bottom superconducting layer was patterned into interconnecting lines as required in device applications, the surface of the YSZ/SiO/sub 2//YSZ on top of the patterned bottom superconducting layer had a roughness of about 500 nm. As a result, the top YBCO was no longer superconducting. Thus, planarization of the patterned bottom superconducting layer becomes a key issue. We have developed a "fill-in and lift-off" process to fill the gap between the patterned bottom superconducting lines with YSZ, As a result, we were able to reduce the surface roughness of the bottom YBCO layer to about 10 nm so the top layer was superconducting with a critical temperature of 87 K.

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