Multibit Sigma-delta Research Articles

Low‐power multibit delta–sigma modulator based on passive and unattenuated summation scheme

AbstractA low‐power multibit delta–sigma modulator (DSM) based on a passive and unattenuated summation scheme is proposed. The summation circuit achieves multiplication of the voltage signal carried on the summation capacitor through a bidirectional sampling technique, thereby compensating for the inherent attenuation caused by passive summation, which eliminates the need for an active operational transconductance amplifier (OTA) to achieve perfect summation. Here, a second‐order DSM based on a 4‐bit first‐order passive noise‐shaping (NS) SAR quantizer is employed to satisfy the SNDR requirements exceeding 100 dB, which validates the reliability of the summation scheme. In addition, a cascoded floating inverter amplifier (FIA) is used as the core OTA to further improve system energy efficiency. Simulation results demonstrate that at a supply voltage of 1.2 V and a bandwidth of 20 kHz, the SNDR reaches 102.62 dB, power consumption is only 148.32 μW, and the Schreier figure‐of‐merit (FoM) of the SNDR is 183.92 dB. The results demonstrate that the proposed DSM has considerable potential for widespread application in the audio domain.

Laser-sound reproduction by pulse amplitude modulation audio streams

Recently, the possibility to reproduce complex continuous acoustic signals via pulsed laser-plasma sound sources was demonstrated. This was achieved by optoacoustic transduction of dense laser pulse trains, modulated via single- or multi-bit Sigma–Delta, in the air or on solid targets. In this work, we extend the laser-sound concept to amplitude modulation techniques. Particularly, we demonstrate the possibility of transcoding audio streams directly into acoustic pulse streams by analog pulsed amplitude modulation. For this purpose, an electro-optic modulator is used to achieve pulse-to-pulse amplitude modulation of the laser radiation, similarly to the multi-level Sigma–Delta method. The modulator is directly driven by the analog input stream through an audio interface. The performance of the system is evaluated at a proof-of-principle level for the reproduction of test audio signals such as single tones, double tones and sine sweeps, within a limited frequency range of the audible spectrum. The results are supported by computational simulations of the reproduced acoustic signals using a linear convolution model that takes as input the audio signal and the laser-generated acoustic pulse profile. The study shows that amplitude modulation allows for significant relaxation of the laser repetition rate requirements compared to the Sigma–Delta-based implementation, albeit at the potential cost of increased distortion of the reproduced sound signal. The nature of the distortions is analyzed and a preliminary experimental and computational investigation for their suppression is presented.

An Intrinsically Linear 13-Level Capacitive DAC for Delta Sigma Modulators

Mismatch of the digital-to-analog converter (DAC) elements is the major limitation for Signal to Noise and Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFDR) in multi-bit Delta Sigma Modulators (DSM). In this article we extend a previously introduced technique to build an intrinsically linear 13 level DAC. An exemplary Switched-Capacitor (SC) 13-levels 20 kHz discrete-time DSM employing this technique is simulated and achieves an SFDR higher than 100 dBc on circuit level in presence of considerable capacitor mismatch. The presented DAC architecture is not limited to be used in a discrete-time modulator, but could also be employed in a Continuous-Time DSM (CTDSM).

Digital Sine Oscillators Based on Higher Order Sigma–Delta Modulation

In this paper, a new class of digital sine oscillators based on higher-order multibit sigma-delta modulation is presented. The samples of a given pure sine signal are quantized, resulting in a pulse-code modulated (PCM) sequence. A numeric condition for oscillation (NCO) based on the PCM signal is disclosed. If the NCO is fulfilled, a system constant <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F</i> with a finite bit width can be derived and a hardware-efficient practical realization of a digital oscillator based on <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> -order sigma-delta modulation is possible. The oscillator output sequence is an <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> -times differentiated version of the PCM signal and thus the PCM signal can be reconstructed by <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> -subsequent accumulations. All signals are absolutely periodic and are represented by binary numbers with well-defined finite bit widths. Initial conditions for the registers of the oscillator are determined. An example for the generation of a high-purity PCM signal with 2048 samples per period is demonstrated. The noise spectrum of this signal is white and the ratio between the mean noise amplitude and the signal amplitude is about one over one billion. The resulting oscillator requires a third order sigma-delta modulator. The chip size is estimated for the oscillator being integrated in a commonly used CMOS technology.

Nonlinearity Mitigation Based on Modulus Pruned Look-Up Table for Multi-Bit Delta-Sigma 32-CAP Modulation in Underwater Visible Light Communication System

Application of light-emitting diodes (LEDs) based visible light communication (VLC) in underwater wireless communication has become a hot topic. However, on the one hand, the performance of underwater VLC (UVLC) system is limited due to power attenuation in water medium. On the other hand, increasing the driving power will induce nonlinearity from the imperfect optoelectronic components. Particularly at high signal amplitude, nonlinearity will become the dominant bottleneck. In this paper, we focus on nonlinearity mitigation method which preprocesses signal at transmitter-side. Multi-bit delta-sigma modulation combined carrier-less amplitude and phase modulation (DSM-CAP) is proposed to obtain quantized signal with lower peak-to-average power ratio (PAPR). Furthermore, as assuming the quantization noise being additive white noise is not appropriate in nonlinearity, modulus pruned weighted look-up table (MP-WLUT) is employed to modify the signal before DSM quantization to mitigate pattern dependent nonlinear distortion. Experimental results indicate that the DSM-CAP has better nonlinearity mitigating performance than normal CAP. At the data rate of about 1.69Gbp/s, utilizing MP-WLUT pre-distorted DSM-CAP an improvement of 1.44 dB Q-factor is realized compared with normal CAP without WLUT, and the size of MP-WLUT can be reduced to 62.5% of the full-size WLUT.

Advanced Mixed Signal Concepts Exploiting the Strong Body-Bias Effect in CMOS 22FDX®

In this article, an overview of the most recent fully-depleted silicon on insulator technology (FD-SOI) design techniques in the field of mixed-signal circuits and systems are given. Cutting edge performance is achieved by using dynamic as well as static body-biasing techniques. 22FDX <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> is a 22nm CMOS FD-SOI technology providing both, a unique wide-band body-bias tuning range in conjunction with minimized parasitic device loads, due to the significant reduced pn junctions in the signal path. As a result, transistor transit frequencies exceeding 400GHz with improved linearity is achieved. With a linear threshold voltage sensitivity of around 75mV per Volt, 22FDX <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> gives designers a competitive additional degree of freedom. After introducing 22FDX <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> , a 5-bit 18.5GS/s flash ADC is presented utilizing body-biasing to generate accurate threshold voltage offsets within the comparators and thus omitting a power-hungry resistive ladder. Then, dynamic body-biasing is used for a 1.5GS/s track-and-hold circuit to improve the bandwidth while the leakage is reduced obtaining 80dBc SFDR up to the fourth Nyquist zone. Furthermore, a 26GHz ring oscillator is presented, which utilize the strong threshold voltage sensitivity to fully compensate corner dependency. Finally, a body-biasing controlled DAC linearization technique for multi-bit Sigma-Delta modulators enabling 90dBc SFDR, as well as a DAC driver termination impedance control for a 6GS/s 10-bit automotive Ethernet SST-DAC-Driver are presented.

An Extremely Linear Multi-Level DAC for Continuous-Time Delta-Sigma Modulators

The nonlinearity of the multi-level digital-to-analog converter (DAC), arising from element mismatches, is a critical issue in the design of multi-bit Delta-Sigma modulators (DSMs). In this brief, we propose an extremely linear multi-level DAC that requires no trimming, calibration, or dynamic element matching for continuous-time DSMs that are sensitive to loop delays. The proposed DAC combines a tri-level switched-capacitor circuit with a pulse-width-modulation (PWM) scheme modified to eliminate the nonlinearity-causing signal-dependent timing of the PWM pulses. Theoretical analysis and Monto-Carlo simulations verifying the linearity of the proposed DAC are presented.

Design and implementation of sigma–delta digital to analog converter

This paper presents the design and implementation of a 16-bit sigma–delta digital to analog converter (DAC) for audio applications. In order to achieve high-order noise shaping without the stability problem inherent in the design of higher order loop, cascade structure may be used. One of the drawbacks in a multi-bit cascaded sigma delta modulator is the un-cancelled noise and the nonlinearity error. The idea of the proposed architecture is to present an improved version of cascaded multi-bit sigma–delta modulator to overcome these problems. Simulation results verify the superiority of the proposed modulator. Sampling rate conversion plays a predominant role in the signal processing and has a strong influence on the overall complexity and cost of efficient sigma–delta DAC. In this paper a technique to examine filter architectures that can be effectively applied in the interpolator design is also presented; the sigma–delta modulator design is implemented on a field programmable gate array (FPGA) for verification purpose and results are presented.

A Multi-bit Delta-Sigma Audio DAC with 120dB Dynamic Range

A Multi-bit Delta-Sigma Audio DAC with 120dB Dynamic Range

A 0.6V 19.5μW 80dB DR ΔΣ Modulator with SA-Quantizers and Digital Feedforward Path

This paper presents a discrete-time multi-bit Delta–Sigma modulator employing successive approximation (SA)-quantizers for bio-signal acquisitions. In the proposed [Formula: see text] modulator, the input signal is separately quantized and the signal summation is performed in the digital domain to avoid the power hungry analog adder. Two SA-quantizers are used in this modulator. One is dedicated to quantize the input signal and the other is to quantize the summation of the integrators’ outputs. Dynamic Element Matching (DEM) technique is used to mitigate the mismatch among the digital-to-analog conversion (DAC) elements. To reduce the complexity of the DEM logic, the 7-bit summed quantizer output is truncated into a 5-bit code before it is fed to the DEM circuits. Double tailed inverter-based op-amp is used in the loop filter for low-voltage operation. Correlated-double-sampling is adopted to enhance the effective gain of the integrator. The proposed modulator is designed and fabricated in a 130-nm CMOS technology. The measurement result shows that the modulator achieves a dynamic range of 80[Formula: see text]dB, a peak SNDR of 77[Formula: see text]dB in a 25[Formula: see text]kHz signal bandwidth at sampling rate of 800[Formula: see text]kHz. The prototype modulator occupies 0.25[Formula: see text]mm2 and consumes only 19.5[Formula: see text][Formula: see text]W from a 0.6[Formula: see text]V supply. The proposed modulator achieves a figure of merit of 67 fJ per conversion step.

Design of 3rd order cascaded multi-bit sigma delta modulator for ADC using internal feedback

This paper presents a new design of third order cascaded multi-bit sigma delta modulator for analogue to digital converter. The proposed modulator is based on the conventional multibit cascaded sigma delta modulator with interstage feedback topology. Sigma delta systems favours a cascaded multi-bit architecture for higher resolution and wider bandwidth with extra effort focusing on suppressing the analogue nonlinearity. One of the major analogue non-idealities in a multi-bit cascaded sigma delta modulator is the DAC nonlinearity errors and one of the drawbacks is that performance will be limited by un-cancelled noise introducing from the nonlinear errors of multi-bit DAC. The idea of proposed architecture is to create extra feedback paths around the modulator to reduce the DAC error. In this paper, an improved version of cascaded multi-bit sigma delta modulator is proposed to overcome these problems. In addition, a third order cascaded low distortion ADC architecture is also proposed. Simulation results verify the superiority of both the proposed modulators.

Design of 3rd order cascaded multi-bit sigma delta modulator for ADC using internal feedback

This paper presents a new design of third order cascaded multi-bit sigma delta modulator for analogue to digital converter. The proposed modulator is based on the conventional multibit cascaded sigma delta modulator with interstage feedback topology. Sigma delta systems favours a cascaded multi-bit architecture for higher resolution and wider bandwidth with extra effort focusing on suppressing the analogue nonlinearity. One of the major analogue non-idealities in a multi-bit cascaded sigma delta modulator is the DAC nonlinearity errors and one of the drawbacks is that performance will be limited by un-cancelled noise introducing from the nonlinear errors of multi-bit DAC. The idea of proposed architecture is to create extra feedback paths around the modulator to reduce the DAC error. In this paper, an improved version of cascaded multi-bit sigma delta modulator is proposed to overcome these problems. In addition, a third order cascaded low distortion ADC architecture is also proposed. Simulation results verify the superiority of both the proposed modulators.

Designs of multi-bit sigma delta modulator

This paper presents new design variants of third order multi-bit sigma delta modulator (SDM): low distortion SDM and cascaded SDM. The proposed modulator based on the conventional SDMsuch L-0MASH(Multi-stAge noise SHaping) and interstage feedback topology. TheMASHSDM is not a single loop system. One of the drawback is that performance is limited by uncancelled noise from the first modulator and interstage feedback topology only cancels nonlinear errors introducing by multi-bitDACin the final stage, but the rest stage still containsDACnonlinearity errors without any noise shaping which still degrade overall system performance. An improved version of cascaded multi-bit SDM is proposed to overcome these problems mentioned above. In addition a third order low distortion SDM is also proposed. Simulation results verify the superiority of the both proposed modulator.

A Multibit Delta–Sigma Modulator With Double Noise-Shaped Segmentation

This brief proposes a low-power architecture for a discrete-time (DT) delta-sigma modulator to take full advantages of increased quantization levels. In the proposed architecture, noise-shaped segmentation is applied to both the quantizer and the feedback digital-to-analog converter to maintain a high resolution and a high linearity and, at the same time, keep the hardware complexity low. This leads to a significantly reduced output swing of the integrator to minimize the slewing-related distortion in a DT implementation. The resulting uniform linear settling behavior can tolerate a relatively large settling error without degrading the performance, which greatly relaxes the bandwidth requirement of the op-amp design. The reduced output swing also allows the use of low-gain amplifiers, which is particularly attractive for an advanced technology in which the intrinsic gain of the transistor is degraded. The proposed architecture is analyzed and verified through simulation.

A low-distortion multi-bit sigma–delta ADC with mismatch-shaping DACs for WLAN applications

A low-distortion feed-forward MASH24b-24b sigma–delta analog-to-digital converter (ADC) for wireless local area network (WLAN) applications was presented. The converter exhibits improved performances than the ADCs which have been presented to date by adding a feedback factor in the second stage and employing a 2nd-order noise-shaping dynamic element matching (DEM) scheme. The feedback factor induces a zero in the noise transfer function (NTF) and therefore improves the in-band signal to noise and distortion ratio (SNDR) of the modulator. The mismatch-shaping DEM was introduced and applied to the 4-bit DACs in this paper to improve the resolution and linearity of the ADC. Fabricated in a 0.18μm CMOS process with single 1.8V supply voltage, the converter achieves a peak SNDR of 85.4dB over a 10MHz bandwidth which implies an effective number of bits (ENOB) of 13.90-bit. The spurious free dynamic range (SFDR) is –94dB for a 1.25MHz@–6dBFS input signal at 160MHz sampling frequency. The occupied area is 0.44mm2 and dissipation power 23.4mW.

A TDC-Based Two-Step Quantizer With Swapper Technique for a Multibit Continuous-Time Delta–Sigma Modulator

A time-to-digital converter (TDC)-based two-step quantizer is proposed for a multibit continuous-time delta–sigma modulator (CTDSM). In the proposed time-domain quantizer, the barrel-shifting operation realizes the dynamic element matching (DEM) function inherently, eliminating an explicit DEM circuit and the associated circuit latency. The two-step quantization scheme further reduces the hardware and power consumption of a multibit TDC quantizer. A swapper technique, in addition to the inherent DEM, is incorporated to randomize the selection of the two banks of digital-to-analog converter cells, which ensure good linearity. A third-order CTDSM incorporating the proposed TDC-based two-step quantizer is fabricated in a 90-nm CMOS process. The modulator achieves a signal-to-noise-and-distortion ratio of 69.6 dB over a 1-MHz signal bandwidth. Operated from 1.2-V analog and 1-V digital supplies, the whole CTDSM consumes 1.79 mW and achieves a figure of merit of 361 fJ/conversion.

Nonlinear Stability Prediction of Multibit Delta–Sigma Modulators for Sinusoidal Inputs

This paper proposes a novel algorithm that can be integrated with various design and evaluation tools, to more accurately and rapidly predict stability in multibit delta-sigma (Δ-Σ) modulators. Analytical expressions using the nonlinear gains from the concept of modified nonlinearity in control theory are incorporated into the mathematical model of multibit Δ-Σ modulators to predict the stable amplitude limits for sinusoidal input signals. The nonlinear gains lead to a set of equations, which can numerically estimate the quantizer gain as a function of the input sinusoidal signal amplitude. This method is shown to accurately predict the stable amplitude limits of sinusoids for second-sixth-order three- and five-level midtread quantizer-based Δ-Σ modulators. The algorithm is simple to apply and can be extended to midrise quantizers or to any number of quantizer levels. The only required input parameters for this algorithm are the number of quantizer levels and the coefficients of the noise transfer function.

Multi-bit Sigma-Delta TDC Architecture with Improved Linearity

This paper describes the architecture and principles of operation of sigma-delta ( ΣΔ) time-to-digital converters (TDC) for high-speed I/O interface circuit test applications. In particular, we describe multi-bit ΣΔ TDC architectures; they offer good accuracy with short testing time. However, mismatches among delay cells in delay lines degrade their linearity. Here we propose two methods to improve the overall TDC linearity: a data-weighted-average (DWA) algorithm, and a self-calibration method that measures delay values using a ring oscillator circuit. Our Matlab simulation results demonstrate the effectiveness of these approaches.

A $\Sigma \Delta$-FIR-DAC for Multi-Bit $\Sigma \Delta$ Modulators

In this paper, a new digital-to-analog converter (DAC) is proposed for multi-bit continuous-time sigma-delta modulators (ΣΔMs). This -finite-impulse-response-DAC (ΣΔ-FIR-DAC) digitally converts the multi-bit output of the quantizer to a 1.5-bit signal at a higher rate and then injects it to the modulator loop filter by using a 1.5-bit DAC. An FIR filter is merged into 1.5-bit DAC to improve the clock jitter insensitivity. Furthermore, a new implementation of ΣΔ-FIR-DAC is presented to reduce the output rate of ΣΔ-FIR-DAC down to the original rate of the modulator. This reduced rate ΣΔ-FIR-DAC (RR-ΣΔ-FIR-DAC) can be used in both continuous-time and discrete-time ΣΔMs. Theoretical analysis supported by simulation results are provided to evaluate the performance, clock jitter immunity and robustness against DAC elements mismatch in the proposed modulators.

A Describing Function Study of Saturated Quantization and Its Application to the Stability Analysis of Multi-Bit Sigma Delta Modulators

Just as their single-bit counterparts, multi-bit sigma delta modulators exhibit nonlinear behavior due to the presence of the quantizer in the loop. In the multi-bit case this is caused by the fact that any quantizer has a limited output range and hence gives an implicit saturation effect. Due to this, any multi-bit modulator is prone to modulator overloading. Unfortunately, until now, designers had to rely on extensive time-domain simulations to predict the overloading level, because there is no adequate analytical theory to model this effect.