Design of 3rd order cascaded multi-bit sigma delta modulator for ADC using internal feedback

Abstract

This paper presents a new design of third order cascaded multi-bit sigma delta modulator for analogue to digital converter. The proposed modulator is based on the conventional multibit cascaded sigma delta modulator with interstage feedback topology. Sigma delta systems favours a cascaded multi-bit architecture for higher resolution and wider bandwidth with extra effort focusing on suppressing the analogue nonlinearity. One of the major analogue non-idealities in a multi-bit cascaded sigma delta modulator is the DAC nonlinearity errors and one of the drawbacks is that performance will be limited by un-cancelled noise introducing from the nonlinear errors of multi-bit DAC. The idea of proposed architecture is to create extra feedback paths around the modulator to reduce the DAC error. In this paper, an improved version of cascaded multi-bit sigma delta modulator is proposed to overcome these problems. In addition, a third order cascaded low distortion ADC architecture is also proposed. Simulation results verify the superiority of both the proposed modulators.