Design and implementation of sigma–delta digital to analog converter

Abstract

This paper presents the design and implementation of a 16-bit sigma–delta digital to analog converter (DAC) for audio applications. In order to achieve high-order noise shaping without the stability problem inherent in the design of higher order loop, cascade structure may be used. One of the drawbacks in a multi-bit cascaded sigma delta modulator is the un-cancelled noise and the nonlinearity error. The idea of the proposed architecture is to present an improved version of cascaded multi-bit sigma–delta modulator to overcome these problems. Simulation results verify the superiority of the proposed modulator. Sampling rate conversion plays a predominant role in the signal processing and has a strong influence on the overall complexity and cost of efficient sigma–delta DAC. In this paper a technique to examine filter architectures that can be effectively applied in the interpolator design is also presented; the sigma–delta modulator design is implemented on a field programmable gate array (FPGA) for verification purpose and results are presented.