Multiphase Buck Converter Research Articles

Generalized State Space Average Model for Multi-Phase Interleaved Buck, Boost and Buck-Boost DC-DC Converters: Transient, Steady-State and Switching Dynamics

This paper presents a generalized state space average model (GSSAM) for multi-phase interleaved buck, boost and buck-boost converters. The GSSAM can model the switching behavior of the current and voltage waveforms, unlike the conventional average model which can model only the average value. The GSSAM is used for the converters with dominant oscillatory behavior such as resonant converters, high current ripple converters, and multi-converter systems. The maximum current and voltage through the system can be predicted by modeling the switching behavior of voltage and current. The GSSAM in the literature is introduced for single-phase converters only, and it is not introduced for multi-phase converters due to the high complexity associated with it. Hence, the GSSAM for multi-phase buck, boost and buck-boost converters are introduced in this paper and the proposed models can fit with converters of any number of phases. The number of operating phases in the multi-phase interleaved converters is proportional with the output power to achieve the maximum efficiency over the operating range. Therefore, the proposed GSSAMs can describe the operation at any number of operating phases with switching dynamics of phases. The proposed GSSAM is validated by comparing the transient and steady-state dynamics between the GSSAM and a switching model from PLECS.

Comprehensive Analysis and Design of Current-Balance Loop in Constant On-Time Controlled Multi-Phase Buck Converter

Constant on-time (COT) controlled multi-phase buck converter has been widely used in high-current applications such as computing devices to achieve high entire-load-range efficiency. However, the literature lacks comprehensive analysis and design guide of the current-balance loop in COT control, resulting in possible low efficiency, per-phase current protection false-trigger, and stability issue. To solve the aforementioned issues, dc inductor current equations and small-signal models are proposed for COT control with the current-balance loop. Current-balance loop gain design guideline is then proposed to achieve accurate dc current balance and stability. Experiment and simulation results verify the analysis and the accuracy of the proposed models.

Markov Chain Modeling for Reliability Analysis of Multi-Phase Buck Converters

In recent years, the structure of multi-phase buck converter also called Interleaved Buck Converter (IBC) has gained considerable attention. The advantages of the IBC in comparison to the conventional Buck converter (CBC) are the lower output current ripple, higher efficiency, fast transient response, lower electromagnetic interference and higher reliability. Since more than one stage is employed in the IBC, this converter is highly reliable. In this paper, the reliability and mean time to failure (MTTF) of the CBC, and two- and three-stage IBCs are figured out. Using the obtained results and considering various scenarios, a comprehensive comparison is provided. In addition, the operation of the converter in case of fault occurrence for high and low capacities is analyzed and reliability is evaluated in each state. The relation between the reliability and temperature of semiconductor elements is discussed. Furthermore, a laboratory-scaled prototype is used to extract the experimental results of the temperature variation of the elements during a fault. Markov model is used to evaluate the analyzed reliability.

Control of a Multiphase Buck Converter, Based on Sliding Mode and Disturbance Estimation, Capable of Linear Large Signal Operation

Power-hardware-in-the-loop systems enable testing of power converters for electric vehicles (EV) without the use of real physical components. Battery emulation is one example of such a system, demanding the use of bidirectional power flow, a wide output voltage range and high current swings. A multiphase synchronous DC-DC converter is appropriate to handle all of these requirements. The control of the multiphase converter needs to make sure that the current is shared equally between phases. It is preferred that the closed-loop dynamic model is linear in a wide range of output currents and voltages, where parameter variations, control signal limits, dead time effects, and so on, are compensated for. In the case presented in this paper, a cascade control structure was used with inner sliding mode control for phase currents. For the outer voltage loop, a proportional controller with output current feedforward compensation was used. Disturbance observers were used in current loops and in the voltage loop to compensate mismatches between the model and the real circuit. The tuning rules are proposed for all loops and observers, to simplify the design and assure operation without saturation of control signals, that is, duty cycle and inductor current reference. By using the proposed control algorithms and tuning rules, a linear reduced order system model was devised, which is valid for the entire operational range of the converter. The operation was verified on a prototype 4-phase synchronous DC-DC converter.

Automating the Design of Asynchronous Logic Control for AMS Electronics

Analog and mixed signal (AMS) electronics becomes increasingly complex and needs to be digitally enhanced by its own control circuitry. The RTL synthesis flow routinely used for digital logic is, however, optimized for synchronous data processing and produces inefficient control for AMS. In this paper, we demonstrate the evident benefits of asynchronous circuits in the context of AMS systems, and propose an asynchronous design for analog electronics (A4A) flow for their specification, synthesis, and formal verification. A library of specialized analog-to-asynchronous (A2A) components is developed for interfacing analog and asynchronous worlds. A4A flow is automated in the Workcraft framework and evaluated using a multiphase buck converter case study, where A2A components are employed to sanitize analog sensor readings. Timing analysis of asynchronous buck control shows improved response time: 4× reaction to high-load and 7× to under-voltage condition, compared with a 333 MHz clocked controller (to achieve a similar response time, a clocked controller would require ~3 GHz frequency). The simulation results of a 4-phase asynchronous buck demonstrate improved voltage ripple and peak current -16% and 12% reduction, respectively. These benefits lead to the higher efficiency of power conversion, and can be traded off for the cost of analog components, e.g., coils. Moreover, the use of the proposed design flow and tools helps to improve design productivity and overall robustness of AMS circuits.

Single-Inductor Multioutput-Level Buck Converter for Reducing Voltage-Transition Time and Energy Overheads in Low Power DVS-Enabled Systems

Dynamic voltage scaling (DVS) is a useful technique to optimize performance and efficiency of CMOS digital processors using dc–dc converters that require to meet extremely fast slew rate demand. However, there exist conflicting design criteria in existing DVS power supply architectures. This paper proposes a single-inductor multioutput-level buck converter for low power DVS-enabled systems. Under the time optimal voltage transition recovery, the proposed architecture: first, achieves the performance much beyond system's physical limits compared to conventional synchronous and multiphase buck converter based architectures; and second, can overcome conflicting power circuit design criteria in existing architectures. Also, a high-resolution quantized voltage can be realized by using a voltage-dithering technique. An analytical framework is considered to formulate various processor and converter-induced energy overheads. A comparative study is shown to evaluate the usefulness of the proposed architecture over the existing approaches under frequent voltage transitions. A prototype single-inductor four-output-level buck converter is tested and the performance improvements are demonstrated using test results.

Comparative study of digital control schemes for interleaved multi-phase buck converters

The increasing amount of required functionality in today’s electronic devices demands for more advanced power supply concepts. A possible solution to increase the performance and efficiency of DC-DC converters is to use multi-phase topologies. These converters employ multiple parallel power stages, hence sharing the total load current. In order to provide a regulated output voltage and equal sharing of the total current, a control loop is an essential part of such a converter. This paper presents three digital control schemes for multi-phase buck converters, namely, a linear voltage mode controller, a combined Ton/Toff control and a non-linear sliding mode control (SMC) law. Experimental results of a two-phase buck converter highlight the effectiveness of more sophisticated controllers and the benefits of multi-phase over single-phase converters.

48-V Voltage Regulator Module With PCB Winding Matrix Transformer for Future Data Centers

Efficient power delivery architecture is gaining more attention in the design of future generations of data centers in order to minimize the ever increasing trend of power consumption. Silicon-based power delivery architectures and designs have already reached a level of maturity in terms of efficiency and density. Recent studies indicate that 48-V voltage regulator modules (VRMs), instead of 12-V VRMs, are deemed a more efficient and cost effective architecture. In this paper a Gallium Nitride (GaN) based design of a two-stage solution is proposed. The first stage is a 48 V/12 V-250 W LLC converter with a matrix transformer design operating at 1.6 MHz with a peak efficiency of 97.3% and a power density of 870 W/in3. The second stage is a 12/1.8 V multiphase buck converter which can be either a conventional silicon-based or a GaN-based design with a higher operating frequency and power density. Furthermore, in this proposed two-stage architecture, a novel light load improvement mechanism is proposed by dynamically changing the bus voltage from 12 to 6 V during light load by which the system can achieve a more than 8% efficiency improvement.

Two-Stage 48 V-12 V/6 V-1.8 V Voltage Regulator Module With Dynamic Bus Voltage Control for Light-Load Efficiency Improvement

The two-stage 48 V-12 V-1.8 V voltage regulator module (VRM) structure is gaining more and more attention in high-end server applications. The LLC converter is the preferred choice for the first conversion stage because it provides the isolated 12-V output efficiently, which is then converted to 1.8 V by the multiphase Buck converter. Since the CPU works in sleep-mode most of the time, the light-load efficiency is very important for energy saving. This paper proposes to change the primary side of the LLC converter from the full-bridge (FB) configuration into the half-bridge (HB) configuration dynamically in the light-load condition, so that the output of the LLC dc transformer (DCX) can be changed from 12 to 6 V. This will increase the overall light-load efficiency significantly due to the reduced core loss of the LLC DCX and the reduced switching loss of the multiphase Buck converter. To achieve a fast transition of the bus voltage between 12 and 6 V, the capacitance for the intermediate bus is properly selected and the optimal trajectory control for transition between the FB configuration and HB configuration is proposed. A high-efficiency high-density 48–12 /6 V LLC DCX is designed, and experiments on the two-stage VRM demonstrate that there is a fast transient response and a more than 10% light-load efficiency improvement.

Parameter-Insensitive Mixed-Signal Hysteresis-Band Current Control for Point-of-Load Converters With Fixed Frequency and Robust Stability

The inductor current ripple under hysteresis current control is sensitive to system as well as controller parameters, which often deviates from the desired band. Thus, a phase-locked-loop (PLL) is employed to regulate the switching frequency over the operating range. Digital platform drastically simplifies this using an all-digital PLL (ADPLL) and offers the controller-tuning flexibility for improved performance. However, the use of uniform voltage-sampling often leads to multilimit cycle instability. This paper proposes a mixed-signal hysteretic current controller (MSHCC) with the digital voltage-loop and the analog current-loop. A digital-to-analog converter is sufficient to generate time-multiplexed current references. This achieves robust stability and parameter-insensitive current ripple by sampling the error-voltage at the rising edge of the high-side gate signal. Stability analysis is carried out using discrete-time models. The proposed MSHCC can be configured to either of the peak, average, or valley current-mode techniques along with the flexibility to adjust the switching frequency using an ADPLL for real-time energy-optimization. The proposed scheme is implemented using an FPGA device and tested on a buck converter prototype. The MSHCC scheme can be extended to a multiphase buck converter.

Current‐balance method for multi‐phase DC–DC buck converters with wide duty ratio applications in both CCM and DCM

To cope with the current imbalance situation of multi-phase buck converters with wide duty ratio range applications in continuous conduction mode (CCM) and discontinuous conduction mode (DCM), a current-balance method is proposed. In CCM, with small power loss, current balance can be achieved by comparing the replica currents flowing through the sensing transistors. In DCM, an additional offset cancellation circuit is designed to eliminate the intrinsic offset voltage mismatch existing in main-loop comparators. Then each phase sequentially performs a switching operation to share the switching stress. Experimental results show that the current imbalance is decreased to 0.15% under duty ratio from 0.1 to 0.75. Load current is well distributed between phases in both the CCM and DCM without tricky implement.

A Simple Sensorless Current Sharing Technique for Multiphase DC–DC Buck Converters

Multiphase buck converters are widely used to power up low-voltage high-current loads, such as microprocessors, battery chargers, hybrid vehicles, among others. For this converter, topology is necessary to guarantee a correct distribution of the total output current among phases in order to ensure proportionality in electrical losses and thermal stresses. So, a current sharing scheme is a desirable part in a multiphase buck converter. Most of the proposed current distribution schemes include sensing circuitry and a current loop for each phase. Nevertheless, by using sensors, control complexity and assembly costs increases proportionally to the number of phases. This paper presents a simple sensorless current sharing algorithm for multiphase buck converters. The proposed technique is based on simple one-time tests by turning-on each phase in order to estimate the parasitic resistance for the turned-on phase. Once the parasitic resistances are known, the duty cycles, which allow for adequate current sharing among phases, are calculated. An extra control algorithm ensures that the compensated duty cycle is applied at the switching node. This extra control loop does not require analog-to-digital converters. Analysis and experimental results of proposed control technique are shown using a five-phase dc-dc buck converter. The proposed algorithm exhibits an adequate distribution of the load current between phases.

Integrated high step-down multiphase buck converter with high power density

A novel integrated implementation of a high step-down multiphase buck for low voltage power supply is presented. The design and test chip measurements of a [10.8,16]V to [0.65,2]V, 2A, 10MHz, 25.6mW/mm2, four-phases single-chip solution are presented with considerations on architecture, passive components, problems related to high frequency integration and relative improvements on power density. The experimental results confirm the theoretical predictions by simulations and are compared with respect to previous discrete implementations and integrated topologies focusing on high step-down conversion and output power. So-called “high step-down multiphase buck” topologies present advantages in terms of extended duty cycle, reduced passive components’ size and reduced switches’ breakdown voltages. However, these topologies require a more complex gate drive structure for their high side switches which are working each on a different voltage domain. A novel drive architecture that eliminates the need of any external auxiliary voltage source, being directly supplied on fractions of the input voltage, is proposed. This architecture provides also a recycling of the gate charge at the turn-off of the switches. Another problem addressed is the start up of the converter, which requires a proper pre-charging of the topology's flying capacitors. Power stage measured waveforms show the correct start-up and steady-state operation of the proposed converter design.

The Design of a Multilevel Envelope Tracking Amplifier Based on a Multiphase Buck Converter

Envelope tracking (ET) and envelope elimination and restoration (EER) are techniques that have gained in importance in the last decade in order to obtain highly efficient radio frequency power amplifier that transmits signals with high peak-to-average power ratio. In this study, a multilevel multiphase buck converter is presented as a solution for the envelope amplifier used in ET and EER. The presented multiphase buck converter generates multilevel voltage using “node” duty cycles and nonlinear control. In this way, the multilevel is implemented using only one simple power stage. However, the complexity of the multilevel converter implementation has been shifted from complicated power topologies to complicated digital control. Detailed discussion regarding the influence of the design parameters (switching frequency, output filter, and time resolution of the digital control) on the performance of the proposed envelope amplifier is presented. The design of the output filter is conducted fulfilling the constraints of the envelope slew rate and minimum driver pulse that can be reproduced. In the cases when these two constraints cannot be fulfilled, they may be relieved by the modified control that is presented and experimentally validated. Finally, in order to validate the concept, a prototype has been designed and integrated with a nonlinear class F amplifier. Efficiency measurements showed that by employing EER, it is possible to save up to 15% of power losses, comparing to the case when it is supplied by a constant voltage. Additionally, adjacent channel power ratio has been measured. The obtained results showed the value higher than 30 dB for signals up to 5 MHz of bandwidth, without using a predistortion technique.

Zero voltage transition–zero current transition pulse‐width modulated multiphase synchronous buck converter with an active auxiliary circuit for portable applications

In this study, a zero voltage transition (ZVT)–zero current transition (ZCT) pulse-width modulated (PWM) multiphase synchronous buck converter (SBC), with an active auxiliary circuit is proposed, that reduces the stresses and enhances the efficiency abating the switching and conduction losses of the converter. The important design feature of ZVT–ZCT PWM multiphase SBC converters is the placement of resonant components that pacifies the switching and conduction losses. Due to the ZVT–ZCT, the resonant components with low values are used that results in the increase of switching frequency. High current multiphase buck converters found applications in the advanced data control, solid state lasers, communication equipment, Pentium processors etc. The ZVT–ZCT operation of the proposed converter is presented through theoretical analysis. A simple design method for the auxiliary circuit is discussed. The characteristics of the proposed converter are verified with the simulation in the PSIM co-simulated with MATLAB/SIMULINK environment and validated with experimental results.

A Cascade Point of Load DC–DC Converter With a Novel Phase Shifted Switched Capacitor Converter Output Stage

This paper presents the analysis, design, modeling and control of a cascaded two-stage step-down dc–dc converter with a conventional synchronous buck converter in the first stage and a new phase shifted switched capacitor (PSSC) buck converter in the second stage. Higher efficiency and higher power density compared to the conventional multiphase buck converter are the prominent features of the proposed architecture which make it suitable as a point of load converter, widely used in powering computing, communication and networking equipment. The first stage buck converter is operated at high switching frequency with extended duty ratio and is designed for high efficiency. The second stage PSSC converter with low input voltage attains high efficiency when operated at a fixed conversion ratio with low switching frequency and a simple constant current charging technique. A laboratory prototype converter achieved a peak efficiency of $86.8\%$ at $30$ -A load current while operating at $12$ -V input voltage and $1.3$ -V output voltage. The capacitor-based output power stage drastically reduces the number of inductors compared to the multiphase buck converter. A low frequency small signal model of the converter and a state feedback controller for the output voltage are developed analytically. The closed-loop transient performance of the converter using this state feedback controller is also verified experimentally.

A 4-Phase 30–70 MHz Switching Frequency Buck Converter Using a Time-Based Compensator

A high switching frequency multi-phase buck converter architecture using a time-based compensator is presented. Efficiency degradation due to mismatch between the phases is mitigated by generating precisely matched duty-cycles by combining a time-based multi-phase generator (MPG) with a time-based PID compensator (T-PID). The proposed approach obviates the need for a complex current sensing and calibration circuitry needed to implement active current sharing in an analog controller. It also eliminates the need for a high resolution analog-to-digital converter and digital pulse width modulator needed for implementing passive current sharing in a digital controller. Fabricated in a 65 nm CMOS process, the prototype multi-phase buck converter occupies an active area of 0.32 mm $^{2}$ , of which the controller occupies only 0.04 mm $^{2}$ . The converter operates over a wide range of switching frequencies (30–70 MHz) and regulates output to any desired voltage in the range of 0.6 V to 1.5 V from 1.8 V input voltage. With a 400 mA step in the load current, the settling time is less than 0.6 $\mu$ s and the measured duty-cycle mismatch is less than 0.48%. Better than 87% peak efficiency is achieved while consuming a quiescent current of only 3 $\mu$ A/MHz.

Multiphase Current-Controlled Buck Converter With Energy Recycling Output Impedance Correction Circuit (OICC)

This study is related to the improvement of the output impedance of a multiphase buck converter with peak current mode control (PCMC) by means of introducing an additional power path, which virtually increases the output capacitance during transients. Various solutions that can be employed to improve the dynamic behavior of the converter system exist, but nearly all solutions are developed for a single-phase buck converter with voltage mode control, while in the voltage regulation module applications, due to the high currents and dynamic specifications, the system is usually implemented as a multiphase buck converter with current mode control to ensure current sharing. The proposed circuit, output impedance correction circuit (OICC), is used to inject or extract a current n – 1 times larger than the output capacitor current, thus virtually increasing n times the value of the output capacitance during the transients. Furthermore, the OICC concept is extended to a multiphase buck converter system and the proposed solution is compared with the system that has n times bigger output capacitor in terms of dynamic behavior and static and dynamic efficiency. The OICC is implemented as a synchronous buck converter with PCMC, thus reducing its penalty on the system efficiency.

The Characteristic Research of Multi-Phase Interleaving Buck-Converter for High Efficiency and Low Ripple for Green Car or Light System

A step-down non-isolated Buck converter is a common and basic topology in the field. We analyzed the Characteristic of Multiphase Interleaved Buck Converter in DCM(Discontinuous Current Mode) and CCM(Continuous Current Mode) for law ripple and high efficiency1). Multiphase buck converter has more advantages than other topology. Input current of converter is divided into each converters because of the structure. it has features of decreasing input current ripple and increasing efficiency of converter. So we can reduce the size of Capacitor and Inductor2). It means that the size of system is also reduced3). The Time Reverse Recovery loss of diode was also affected4)5), the TRR loss was confirmed to be negligible in the 120kHz 8 Phase case despite the CCM situation. In this study, the effects of the loss factors were analyzed on the efficiency of the multiphase interleaving buck converter in DCM and CCM, and it would be helpful to design a more efficient converter by effectively controlling the factors of each loss. At least, we tested the performance of the analyzed system with PSpice.

An Experimental Approach for Locating the Current Distribution in Multiphase Buck Converters

The objective of this paper is to present a methodology for identifying the current flow in the capacitors of a multiphase buck converter by synchronously measuring the capacitor currents. A multiphase buck converter uses multiple parallel buck converters with different switching times to source a large amount of current. Currents in the primary capacitors of a multiphase buck converter are drawn by all phases of the converter; however, the phases switch asynchronously. Synchronizing to the switching of a specific phase reveals how the current from that phase is distributed among the capacitors throughout a circuit board. The proposed measurement method is illustrated by comparing an initial printed circuit board design to a new design to show the effect of better capacitor placement and the addition of a ground plane. The new design confines the phase currents to the capacitors close to the field effect transistors of the specific phase.