Multi-objective Design Space Exploration Research Articles

Decomposition based estimation of distribution algorithm for high-level synthesis design space exploration

High-Level Synthesis (HLS) has evolved significantly due to the increasing complexity of integrated circuit design and the demand for efficient design methodologies. HLS, which raises the abstraction level of design specification, allows designers to focus on hardware functionality, thus enhancing productivity and reducing verification efforts. However, a key challenge in HLS is efficiently exploring the vast design space to find the Pareto-optimal designs. In this paper, we introduce a novel approach for multi-objective design space exploration in HLS. Our methodology decomposes the design space exploration problem into simpler sub-problems using the Multi-Objective Evolutionary Algorithm based on Decomposition (MOEA/D) framework and utilizes the Estimation of Distribution Algorithm (EDA) to build a probabilistic model for generating candidate solutions, thereby reducing the required number of expensive synthesis runs. Experimental results show that the proposed method has a faster convergence speed and reduces the number of syntheses by 24.34% to 32.01%, which significantly outperforms state-of-the-art works. Our approach achieves superior Pareto fronts with the lowest average ADRS value, outperforming Lattice-expl, ϵ -Constraint GA, and NSGA-II by 85.64%, 39.90%, and 33.31% respectively.

MoDSE: A High-Accurate Multiobjective Design Space Exploration Framework for CPU Microarchitectures

MoDSE: A High-Accurate Multiobjective Design Space Exploration Framework for CPU Microarchitectures

In-depth Multi-Objective charge pump design space exploration towards the automatic synthesis of power management units

The inclusion of automation mechanisms in the intricate design of power management units (PMUs) is long pursued in industry. This paper addresses a mixed-signal design flow whose purpose is to automatically produce, from the system-level to the ready-for-tape-out layout, complex PMUs when given a set of specifications. Particularly, in that flow, at the IP level, the proper analysis of the design tradeoffs is tedious and impractical, as a large amount of conflicting performance figures obtained from transient analysis for typical and multiple process/temperature corners, must be considered simultaneously. Therefore, it is common for the design cycle of a single integrated charge pump required in a state-of-the-art PMU to surpass a full month, depending on the intended technology, devices’ types and operation voltages. Additionally, by the end of this process, circuit designers often end up with a limited vision of the attainable performances. However, due to the recent improvements in computational power of modern workstations, optimization-based techniques with expensive evaluation mechanisms are now perceived as a potential solution to pursue optimal sizing and layout. Therefore, an academic electronic design automation tool is adapted and applied to explore the performance boundaries of a charge pump in a 180-nm technology node and determine the optimal tradeoffs between performance and the, severely constrained, layout area. In the last step, a worst-case corner optimization on a 45- and 99- dimensional design and performance spaces, respectively, derived from 9 time-consuming transient analysis of each candidate solution, produced 35 design solutions that provide a thorough analysis between worst-case efficiency, voltage drop, and rise and fall times, impossible to perform in the manual design. The obtained insights on the design space were used to speed-up the process of devising a solution for tape-out.

IronMan-Pro: Multiobjective Design Space Exploration in HLS via Reinforcement Learning and Graph Neural Network-Based Modeling

Despite the great success of high-level synthesis (HLS) tools, we observe several unresolved challenges: 1) the high-level abstraction of HLS programming styles sometimes conceals optimization opportunities; 2) the actual quality of resulting RTL designs is hard to predict; and 3) existing HLS tools do not provide flexible tradeoff (Pareto) solutions among different objectives and constraints. To this end, we propose an end-to-end framework, namely, IronMan-Pro. The primary goal is to enable a flexible and automated design space exploration (DSE), to provide either optimized solutions under user-specified constraints or Pareto tradeoffs among different objectives (such as resource types, area, and latency). IronMan-Pro consists of three components: 1) GPP, a highly accurate graph-neural-network-based performance and resource predictor; 2) RLMD, a reinforcement-learning-based multiobjective design exploration engine for optimal resource allocation strategies, aiming to provide Pareto solutions among different objectives; and 3) CT, a code transformer to assist RLMD and GPP, which extracts the data flow graphs from original HLS C/C++ and automatically generates synthesizable code with optimized HLS directives. Experimental results show that, 1) GPP achieves high prediction accuracy, reducing the prediction errors of HLS tools by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10.9\times $ </tex-math></inline-formula> in resource utilization and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5.7\times $ </tex-math></inline-formula> in critical path (CP) timing; 2) compared with meta-heuristic-based techniques, IronMan-Pro generates superior solutions improving resource utilization by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$16.0\% \sim 29.5\%$ </tex-math></inline-formula> and CP timing by 7.6%–16.5%; and 3) under user-specified constraints, IronMan-Pro can find satisfying solutions over 96% of the cases, more than twice as many as that of meta-heuristic-based techniques and with a speedup of up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$400\times $ </tex-math></inline-formula> . This work demonstrates the great potential of applying machine learning algorithms in the electronic design automation domain, especially for the hard-to-solve problems, such as timing estimation and optimization. IronMan-Pro is available at <uri xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">https://github.com/lydiawunan/IronMan</uri> .

HARDeNN: Hardware-assisted attack-resilient deep neural network architectures

We propose HARDeNN, a low-overhead end-to-end inference accelerator methodology to armor the underlying pre-trained neural network architecture against black-box non-input adversarial attacks. In order to find the most vulnerable neural network architectures parameters, a hardware-assisted fault injection tool and a statistical stress model have been proposed to synergy uniform fault assessment across layers and targeted in-layer fault assessment to realize a holistic, rigorous fault evaluation in NN topologies susceptible to non-input adversarial black-box attacks. The key observation from the assessment shows that the weights and activation functions are the most vulnerable neural network parameters that are susceptible to both single-bit and multiple-bit flip attacks. Concerning the aforementioned parameters, a multi-objective design space exploration is conducted to find a superior design under different resource constraints. The error-resiliency magnitude offered by HARDeNN can be adjusted based on the given boundaries. The experimental results show that HARDeNN methodology enhances the error-resiliency magnitude of cnvW1A1 by 17.19% and 96.15% for 100 multi-bit upsets that target weight and activation layers, respectively, during CIFAR-10 classification.© 2017 Elsevier Inc. All rights reserved.

PGOpt: Multi-objective design space exploration framework for large-Scale on-chip power grid design in VLSI SoC using evolutionary computing technique

Design of the power grid network (PGN) of a VLSI chip is a challenging task because of the increase in network complexity. Due to the presence of resistances of the metal lines of the PGN, voltage drops occur in the form of IR drop, which can change the voltage level of underlying logic circuits, resulting in malfunction of the System-on-Chip (SoC). The IR drop also depends upon different reliability constraints, and violation of those constraints can deteriorate the IR drop much more. Subsequently, a significant objective while designing a PGN is to reduce the IR drop without violating the reliability constraints. IR drop also affects the timing of the critical path of the circuits. Over the past two decades, several works have been proposed to optimize the PGN by minimizing metal area considering the IR drop as a design constraint. One of the widely accepted IR drop minimization practices is by increasing the metal widths, which in turn increases the metal area. As a result, the area of the chip increases, which manifests that the primary design objectives, i.e., IR drop and metal routing area, are conflicting in nature. Therefore, these two conflicting design objectives need to be accommodated while designing the PGN in order to optimize the reliability and the yield of the chip. In this work, for the first time, we propose a multiobjective design space exploration framework for the power grid design, which deals with reliability and yield. We have studied various design aspects to determine a trade-off between these two critical conflicting design objectives by developing an optimization framework using the evolutionary algorithmic technique. Results on the standard power grid benchmarks demonstrate that our proposed framework helps in a reliable PGN design with high yield.

CSMO-DSE

Determining the optimal microarchitecture configuration of a processor at the early stages of design is undeniably a challenge. Due to many parameters at the microarchitecture level, finding the proper combination of these parameters to arrive at a balanced design is difficult. Application-specific Design Space Exploration (DSE) is even more difficult, since the property of application needs to be considered during the DSE process. Improving the speed and accuracy of the DSE process remains a particular challenge in microprocessor design. In this article, we propose a novel processor DSE methodology based on criticality and sensitivity analysis, named Criticality and Sensitivity-based Multi-Objective DSE (CSMO-DSE). In our methodology, a dependence-graph is derived from the profile generated by running a program on an instrumented cycle-accurate microprocessor simulator. Then, the criticality of the processor’s performance events is obtained through critical path analysis. The sensitivity of microarchitecture parameters to various performance events is also analyzed. Then, this information is used to optimize performance, power/area, and energy efficiency of the design. Experiments with SPEC 2006 show that CSMO-DSE methodology is 4.73× faster than the baseline DSE methodology and that the quality of result (QoR) is better than the baseline methodology for all the benchmark programs.

Estimation of distribution-based multiobjective design space exploration for energy and throughput-optimized MPSoCs

Modern multicore architectures comprise a large set of components and parameters that require being matched to achieve the best balance between power consumption and throughput performance for a particular application domain. The exploration of design space for finding the best power throughput trade-off is a combinatorial optimization problem with a large number of combinations, and. in general, black its solution is prohibitively difficult to be explored exhaustively. However, fortunately, evolutionary algorithms (EAs) have the potential to efficiently solve this problem with reasonable computational complexity. In this paper, we consider a multiobjective design space exploration (DSE) problem with two conflicting objectives. The first objective corresponds to power consumption minimization while the second objective relates to throughput maximization. We approach this problem by employing the estimation of distribution algorithm (EDA), which belongs to the family of EAs. The proposed EDA-based DSE (EDA-DSE) scheme efficiently selects the design parameters (i.e. cache size, number of cores, and operating frequency) with an efficient power through put ratio. The proposed scheme is verified using cycle accurate simulations over a set of benchmarks and the simulation results show a significant reduction in energy delay product for all benchmark applications when compared to the default baseline configuration and genetic algorithm.

MOOS

The growing needs of emerging applications has posed significant challenges for the design of optimized manycore systems. Network-on-Chip (NoC) enables the integration of a large number of processing elements (PEs) in a single die. To design optimized manycore systems, we need to establish suitable trade-offs among multiple objectives including power, performance, and thermal. Therefore, we consider multi-objective design space exploration (MO-DSE) problems arising in the design of NoC-enabled manycore systems: placement of PEs and communication links to optimize two or more objectives (e.g., latency, energy, and throughput). Existing algorithms to solve MO-DSE problems suffer from scalability and accuracy challenges as size of the design space and the number of objectives grow. In this paper, we propose a novel framework referred as Multi-Objective Optimistic Search (MOOS) that performs adaptive design space exploration using a data-driven model to improve the speed and accuracy of multi-objective design optimization process. We apply MOOS to design both 3D heterogeneous and homogeneous manycore systems using Rodinia, PARSEC, and SPLASH2 benchmark suites. We demonstrate that MOOS improves the speed of finding solutions compared to state-of-the-art methods by up to 13X while uncovering designs that are up to 20% better in terms of NoC. The optimized 3D manycore systems improve the EDP up to 38% when compared to 3D mesh-based designs optimized for the placement of PEs.

Grey Wolf Optimizer Driven design space exploration: A novel framework for multi-objective trade-off in architectural synthesis

Abstract Initiating Design Space Exploration (DSE) procedure during architectural synthesis is a highly intricate and tedious process. It involves optimal arrangement of resource utilizations within a design search space to resolve conflicting objectives of power-performance as well as area occupied by different types of resources. To arrive at an arrangement with minimum completion time among all of the permuted arrangements is a Non-Polynomial-hard problem. The problem becomes acute when it involves multi-objectives, as in the case of DSE for ensuring reliable power-performance-area trade-off of application specific processors. Many heuristic algorithms are being considered to derive an optimal solution for this multi-objective DSE procedure. A comprehensive mapping process and reliable solution evaluation approach called Grey Wolf Optimizer Driven DSE (GWO-DSE) is proposed in this article. The contributions of the article are as follows: i) Introduction of a novel GWO-DSE methodology for power-performance-area trade-off ii) Unique solution evaluation methodology called Utility Coefficients and Utility Ranking iii) Unique fitness evaluation function Grey wolf optimizer iv) Comparative benchmarks using digital filter transfer functions v) Substantial improvement in solution arrival within search space (average > 51%) and reduction in exploration time (>89%) when compared to recent DSE approaches for the tested benchmarks.

Multi-objective design space exploration for system partitioning of FPGA-based Dynamic Partially Reconfigurable Systems

Dynamic Partial Reconfiguration (DPR) enables resource sharing in FPGA-based systems. It can also be used for the mitigation of aging-related permanent faults by increasing the number of redundant Partially Reconfigurable Regions (PRRs). Normally, these PRRs are able to host any of the Partially Reconfigurable Modules (PRMs), or tasks, at one particular instance. This kind of system is called homogeneous. However, the FPGA resource constraints limit the amount of homogeneous redundancy that can be used and hence affect the lifetime of the system. This issue can be addressed by utilizing the heterogeneous approach where each PRR now only hosts a subset of the tasks. Further, the deadlines of the applications must also be taken care of in the design phase to decide the mapping and scheduling of tasks to PRRs. To this end, we propose an application-specific multi-objective system-level design methodology to determine the appropriate number of PRRs and the mapping and scheduling of tasks to the PRRs. Specifically, we propose a lifetime-aware scheduling method that maximizes the system's mean time to failure (MTTF) with different tolerances in the makespan specification of an application. We use the scheduler along with an automated floorplanner for design space exploration at design-time to generate a feasible heterogeneous PRR-based system. Our experiments show that the heterogeneous systems can offer more than 2x lifetime improvement over homogeneous ones. It also offers better scaling with increased tolerance in makespan specification.

ReDO: Cross-Layer Multi-Objective Design-Exploration Framework for Efficient Soft Error Resilient Systems

Designing soft errors resilient systems is a complex engineering task, which nowadays follows a cross-layer approach. It requires a careful planning for different fault-tolerance mechanisms at different system's layers: starting from the technology up to the software domain. While these design decisions have a positive effect on the reliability of the system, they usually have a detrimental effect on its size, power consumption, performance and cost. Design space exploration for cross-layer reliability is therefore a multi-objective search problem in which reliability must be traded-off with other design dimensions. This paper proposes a cross-layer multi-objective design space exploration algorithm developed to help designers when building soft error resilient electronic systems. The algorithm exploits a system-level Bayesian reliability estimation model to analyze the effect of different cross-layer combinations of protection mechanisms on the reliability of the full system. A new heuristic based on the extremal optimization theory is used to efficiently explore the design space. Two exploration strategies are proposed. The first strategy aims at optimizing the reliability of the system alone. It is suited in those cases in which reaching a given reliability target is the sole goal. It focuses on finding a reduced set of system's components that, when protected, allow the designer to reach the desired reliability level. As a positive effect, by reducing the number of protected components, the overhead introduced by the fault tolerance techniques is reduced as well. The second strategy jointly considers the effect that the introduced fault-tolerance mechanisms have on the execution time, power, hardware area and software size. This strategy supports the exploration of the design space setting multiple objectives on different design dimensions. An extended set of simulations shows the capability of this framework when applied both to benchmark applications and realistic systems, providing optimized systems that outperform those obtained by applying state-of-the-art cross-layer reliability techniques.

Evolutionary multi-objective multi-architecture design space exploration methodology

The design of revolutionary aerospace vehicles is characterized by large design spaces, a lack of established baselines, and some uncertainty in the design and regulatory requirements that such vehicles will need to meet. A new evolutionary multi-architecture multi-objective optimization algorithm is presented to support design concept selection when faced with such challenges. The proposed approach allows designers to efficiently and exhaustively generate variable-oriented architectures that can be further optimized and compared. It provides a dynamic decision-making environment able to identify trends and trade-offs, and prioritize designs. The application of the proposed methodology to suborbital vehicles highlights key promising technological enablers, which can be leveraged to design high-performance and robust concepts.

DeSpErate++: An Enhanced Design Space Exploration Framework Using Predictive Simulation Scheduling

Exploring the design space of computer architectures generally consists of a trial-and-error procedure where several architectural configurations are evaluated by using simulation techniques. The final goal of the multiobjective design space exploration (DSE) process is the identification of architectural configurations optimal for a set of target objective functions, typically power consumption, and performance. Simulations are computationally expensive making it rather hard to efficiently explore the design space to identify high-quality configurations in an acceptable exploration time when relying solely on a single-core machine to run simulations. To tackle this problem, engineers proposed solutions based on either: 1) the use of approximate analytic performance models to prune the suboptimal regions of the design space by reducing the number of simulations to run or 2) the use of parallel computing resources to run different simulations concurrently. In this paper we demonstrate that, to efficiently speedup the DSE process while fully exploiting the parallel computing infrastructure, we need to combine the two techniques together in a structured manner. In this paper, we investigate this issue and we propose a DSE solution that exploits approximate analytic prediction models to improve the simulation schedule on a parallel computing environment rather than to prune the number of simulations. Experimental results demonstrate that the proposed technique provides a speedup from 1.26× to 4× with respect to other parallel state-of-the art DSE techniques.

MO-PSE: Adaptive multi-objective particle swarm optimization based design space exploration in architectural synthesis for application specific processor design

Architectural synthesis has gained rapid dominance in the design flows of application specific computing. Exploring an optimal design point during architectural synthesis is a tedious task owing to the orthogonal issues of reducing exploration time and enhancing design quality as well as resolving the conflicting parameters of power and performance. This paper presents a novel design space exploration (DSE) methodology multi-objective particle swarm exploration MO-PSE, based on the particle swarm optimization (PSO) for designing application specific processor (ASP). To the best of the authors’ knowledge, this is the first work that directly maps a complete PSO process for multi-objective DSE for power-performance trade-off of application specific processors. Therefore, the major contributions of the paper are: (i) Novel DSE methodology employing a particle swarm optimization process for multi-objective tradeoff, (ii) Introduction of a novel model for power parameter used during evaluation of design points in MO-PSE, (iii) A novel fitness function used for design quality assessment, (iv) A novel mutation algorithm for improving DSE convergence and exploration time, (v) Novel perturbation algorithm to handle boundary outreach problem during exploration and (vi) Results of comparison performed during multiple experiments that indicates average improvement in the quality of results (QoR) achieved is around 9% and average reduction in exploration time of greater than 90% compared to recent genetic algorithm (GA) based DSE approaches. The paper also reports results based on the variation and impact of different PSO parameters such as swarm size, inertia weight, acceleration coefficient, and termination condition on multi-objective DSE.

A parallel and distributed meta-heuristic framework based on partially ordered knowledge sharing

We propose a new distributed and parallel meta-heuristic framework to address the issues of scalability and robustness in the optimization problem. The proposed framework, named PADO (Parallel And Distributed Optimization framework), can utilize heterogeneous computing and communication resources to achieve scalable speedup while maintaining high solution quality. Specifically, we combine an existing meta-heuristic framework with a loosely coupled distributed island model for scalable parallelization. Based on a mature sequential optimization framework, we implement a population-based meta-heuristic algorithm with an island model for parallelization. The coordination overhead of previous approaches is significantly reduced by using a partially ordered knowledge sharing (POKS) model as an underlying model for distributed computing. The resulting framework can encompass many meta-heuristic algorithms and can solve a wide variety of problems with minimal configuration. We demonstrate the applicability and the performance of the framework with a traveling salesman problem (TSP), multi-objective design space exploration (DSE) problem of an embedded multimedia system, and a drug scheduling problem of cancer chemotherapy.

VMODEX: A novel visualization tool for rapid analysis of heuristic-based multi-objective design space exploration of heterogeneous MPSoC architectures

System-level computer architecture simulations create large volumes of simulation data to explore alternative architectural solutions. Interpreting and drawing conclusions from this amount of simulation results can be extremely cumbersome. In other domains that also struggle with interpreting large volumes of data, such as scientific computing, data visualization is an invaluable tool. Such visualization is often domain specific and has not become widely studied and utilized for evaluating the results of computer architecture simulations. In this paper, we introduce our novel interactive visualization tool, called VMODEX, which is developed to support system-level design space exploration of MPSoC architectures. In our tool, the design space is modeled as a tree in which both the design parameters and criteria are shown in a single view. VMODEX is able to handle large design spaces and allows designers to look at the data from different perspectives and at multiple levels of abstraction. Due to the exponential design space in real problems and multiple criteria to be considered, heuristic searching algorithms are often used to trim down a large design space into a finite set of points and provide the designer a set of tradable solutions with respect to the design criteria. In VMODEX, besides the techniques provided for visualizing the DSE results, additional capabilities are developed to understand the dynamic search behavior of heuristic searching algorithms.

A Novel Design Methodology for Implementing Reliability-Aware Systems on SRAM-Based FPGAs

This paper presents a novel design flow for the implementation of digital systems onto SRAM-based FPGAs with soft error mitigation properties. Traditional fault detection/tolerance techniques are coupled with the device dynamic reconfiguration property to achieve soft error mitigation capabilities, and are applied to the single component, to groups of components or to the entire system, based on the most convenient trade-off with respect to a set of parameters. The design flow performs a two-steps multiobjective design space exploration, driven by a cost function taking into account resource utilization, area, and reconfiguration time. A floorplanning based on precise FPGA resource models is introduced to guarantee the feasibility of the hardened solution, identifying a convenient mapping onto the heterogeneous reconfigurable fabric. Experimental results show that the achieved solutions, aimed at achieving a prompt, "on demand” recovery when fault occurs, are characterized by a reduction in reconfiguration time that is higher than 80 percent, a significant improvement with respect to classical solutions.

Multi-objective efficient design space exploration and architectural synthesis of an application specific processor (ASP)

As the growth of system complexity rapidly increases, the gap between Electronic System Level (ESL) and the Register Transfer Level (RTL) must be filled. Currently, Very Large Scale Integration (VLSI) and System-on-Chip (SoC) designs are multi-objective in nature, requiring simultaneous fulfillment of multiple parameters. Extensive research on Design Space Exploration (DSE) problems and synthesis of an application specific processor (ASP) design have been done until now but none of the prior works have focused explicitly on integrating a fast multi-objective architecture exploration mechanism with the architectural synthesis stages to formalize the design methodology of an application specific processor in case of multiple objectives. This paper proposes a design methodology of a multi-objective application specific processor by integrating an efficient multi-objective (area occupied, execution time and power consumption) exploration approach with the architecture synthesis process, useful for portable devices and many high end applications. The formalized steps of the design methodology for the ASP guarantees the designer an error free approach to design the system with strict limitations on compound operational constraints. The results of implementation of the designed ASP using the proposed design methodology in FPGA and ASIC have also been shown.

A High-level Synthesis Design Flow from ESL to RTL with Multi-parametric Optimization Objective

High-level synthesis (HLS) has emerged as the most sophisticated way to bridge the gap between electronic system level (ESL) and its respective structural building block at the register transfer level (RTL). As the growth of system complexity rapidly increases, the gap between high level and RTL needs to be filled. Much advancement has been made in the area of HLS, but none of the works have focused on a formal design methodology that bridges the gap from ESL to RTL considering multi-parametric optimization requirements. This paper exclusively focuses on the formal steps required for multi-parametric optimized HLS design flow. This is significant for industrial projects as well as for the development of fully automated HLS tools for the current generation of portable devices and high-end applications. The design flow initiates with the mathematical model of the application, performs multi-objective design space exploration and finally shows all the steps necessary after exploration for the HLS design. This paper explicitly focuses on highlighting the design flow with optimization of three parameters area, execution time and power consumption during HLS design while working under the prerequisite of stringent operational constraints. The implementation of the proposed method on Field-programmable Gate Array and the chip layout generation will also be presented.