Multilevel Topology Research Articles

Optimisation of total harmonic distortion using carrier-based PWM techniques for nested multilevel inverter topologies

This paper presents the design and simulation of multilevel inverter topologies configuring nested arrangement. It has the remarkable feature of reduced number of diodes and concomitantly higher efficiency compared to the neutral-point clamped (NPC) inverter topology. The simulation of nested multilevel topology is fulfilled for four, five, six, seven, eight and nine output voltage levels having connected with a three phase star connected RL load. The performance comparison for different output voltage levels is accomplished in terms of total harmonic distortion (THD). The carrier-based sinusoidal PWM techniques, namely, phase disposition (PD), phase opposition disposition (POD) and alternative phase opposition disposition (APOD) are adopted here in order to reduce harmonic distortion in the output voltage as well as load current. The harmonic analysis is carried out through FFT analysis. The simulation is performed using MATLAB/Simulink software version R2012b.

A Review on Reduced Switch Count Multilevel Inverter Topologies

Multilevel Inverters (MLIs) are becoming more and more popular in medium and high power applications. This is due to several inherent advantages of MLI over two-level inverters such as high-quality output, lower device ratings, and several others. While the classical topologies are still having applications in most of the key areas, there is a growing interest in newer multilevel topologies with an objective of reducing power semiconductor device count, gate drivers and/or isolated DC sources. In this paper, a comprehensive review of some of the recently proposed newer multilevel inverter topologies with the abovementioned objectives is presented. In this article, a detailed investigation in terms of total power semiconductor switch count, number of DC sources, passive component requirement, highest switch voltage rating, total standing voltage etc. has been presented.

Asymmetrical Three-Level Inverter SiC-Based Topology for High Performance Shunt Active Power Filter

Power quality conditioner systems, such as shunt active power filters (SAPFs), are typically required to have low power losses, high-power density, and to produce no electromagnetic interference to other devices connected to the grid. At the present, power converters with such a features are built using multilevel topologies based on pure silicon semiconductors. However, recently new semiconductors that offer massive reduction of power losses such as silicon carbide (SiC) MOSFETs have been introduced into the power electronics field. In the near future, the applications that demand the highest performance will be powered by multilevel converters based on SiC. In this paper a highly efficient three-level (3L) topology based entirely on silicon carbide (SiC) semiconductors for a SAPF is presented and analyzed in great detail. Furthermore, the proposed topology is compared with other full SiC-based conventional topologies: two level (2L), three-level T-type (3L-TNPC), and three-level neutral-point-clamped (3L-NPC) in terms of efficiency. The proposed asymmetrical topology has an efficiency superior to conventional all SiC 2L and 3L power circuits when the pulse or switching frequency of the system is set higher than 60 kHz. Further, for high current ratings, the asymmetrical topology has the advantage that it can be built just by cascading two half-bridge SiC modules.

Electric network topology and method of transmission of electric energy

The purpose of the work is to reduce losses and increase energy saving in electric networks. To achieve this goal, a multilevel topology of the electrical network and an asynchronous method for transferring electrical energy between nodes including a load, energy sources, energy storage devices connected in an appropriate manner are proposed. It is shown by the mathematical method that this network topology allows using energy storage devices controlled appropriately and using tele-information technologies to optimize the balance of electric energy in the network, achieving equality of the generated and consumed electricity. Such a network topology and a method of transmitting electrical energy can be the basis of digital technologies in the energy sector (ENERNET).

Design and Control of a GaN-Based, 13-Level, Flying Capacitor Multilevel Inverter

Multilevel topologies are an appealing method to achieve higher power density converters for both mobile and stationary systems. This article discusses the design and high-performance hardware implementation of a 13-level, flying capacitor multilevel (FCML) inverter. Derivation of flying capacitor sizing for ac output voltages (for an arbitrary level FCML) is provided. Operating from an 800- $V_{\text {dc}}$ bus, this hardware prototype utilizes switch modules with 100-V rating. Moreover, a 120-kHz switching frequency is enabled through the use of gallium nitride (GaN) FETs and the development of custom-integrated switching cells, which reduce commutation loop inductance and allow for a modular design. The frequency multiplication effect of FCML inverters allows the output inductor of the inverter to be made exceptionally small ( $4.7~\mu \text{H}$ ) while maintaining a 0.7% total harmonic distortion (THD) due to the 1.44-MHz effective inductor ripple frequency.

Model Predictive Current Control of a Seven-Level Inverter With Reduced Computational Burden

Multilevel topologies gained considerable attention in medium-voltage high-power applications due to their advantages over classic two-level inverters, such as lower loss, higher power quality, and eliminating interface transformers. Moreover, vast research has been done in order to improve the control of the power converters to achieve more efficient and simple controllers. Model predictive control (MPC) is one of the control techniques that has been widely used in power electronics recently due to its advantages, such as fast dynamic response, no need for PI regulators and pulsewidth modulation blocks, and capability of nonlinearity inclusion. On the other hand, the high number of calculations especially for higher level topologies is the disadvantage of this approach. This article presents a new finite control set MPC (FCS-MPC) approach for a seven-level topology. This approach reduces the number of calculations significantly compared to conventional FCS-MPC. Applying the computational efficient FCS-MPC to control the output current and flying capacitors voltages' of the seven-level topology reduces the number of calculations from 12 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> to 36, whereas the execution time is reduced six times. Moreover, simulation and experimental results have been shown to demonstrate the performance and feasibility of the developed control method applied to a seven-level topology.

Research on a multilevel corrector magnet power supply based on a buck cascade circuit

To solve the contradiction between the response speed and output stability of a fast corrector magnet power supply, a topology based on the buck cascade circuit is used and tested in this paper. A multilevel circuit is realized with only a small number of switching metal–oxide–semiconductor field effect transistors (MOSFETs). This multilevel topology allows for better response speeds and a lower output current ripple than conventional H-bridge topologies. This article introduces the design concept based on the buck cascade circuit in detail and carries out a simulation analysis. Finally, a prototype is fabricated according to the design principle, and the results of the prototype test are consistent with the simulation results.

Systematic Synthesis and Derivation of Multilevel Converters Using Common Topological Structures With Unified Matrix Models

Multilevel converters (MLCs) have been increasingly adopted in both low-power low-voltage systems and high-power high-voltage applications. In recent years, many new topologies have been proposed, and a few of them have been successfully implemented in industry. While searching for new topologies, synthesis and derivation principles of multilevel topologies are critical for converter design. In this article, a generalized synthesizing approach of multilevel topologies is proposed and analyzed with the considerations of the voltage source, current source, and matrix-type MLCs. Based on the proposed method, the topological relationship among these three types MLCs is revealed through the stage-based common circuit structure. In addition to the graphic-based approach, a mathematical approach is proposed for representing the MLC topologies in this work. The matrix-based model is utilized to unify and verify the derivation and simplification process in a systematic way through many MLC examples in this article. Finally, demonstration examples are presented to show how the proposed principles can be used to derive new topologies covering five-level to nine-level converters. With the ever-increasing research efforts on MLCs, it is hoped that this article can provide a new approach that inspires the development of more interesting and practical MLC topologies for various applications.

Design and analysis of Impedance Source based Asymmetric Inverter for PV application

A novel Impedance source seven level Asymmetric Multilevel topology for PV system is presented here. It comprises of a Quasi Z source network and Asymmetric Multilevel Inverter (QZ-AMLI) to synthesize better quality output with low THD. Quasi Z Source Converter (QZSC) with large voltage gain provides a positive boost voltage to an asymmetric multilevel inverter. Asymmetric structure offers large output levels with a smaller number of switches and input sources. QZS network parameters provide a regulated DC supply to the Asymmetric Multilevel inverter (AMLI). DC input magnitude of the inverter is decided by an algorithm. Switching signals are applied in proper sequence to generate required magnitude at the AC output. Regulated DC output voltages of 16V and 32V are obtained at the output of QZSC1 and QZSC2. 7 level inverter output with a magnitude of 48V is obtained by simulation using Matlab /Simulink. The system ensures lower switching losses, reduced gate drive circuitry and improved harmonic profile. Reduced switch and filter requirements lessen the cost of the system.

Experimental Characterization of Silicon and Gallium Nitride 200 V Power Semiconductors for Modular/Multi-Level Converters Using Advanced Measurement Techniques

The increasing demand for higher power densities and higher efficiencies in power electronics, driven by the aerospace, electric vehicle, and renewable energy industries, encourages the development of new converter concepts. In particular, modular and/or multi-level (M/ML) topologies are employed to break the performance barriers of the state-of-the-art power converters by simultaneously reducing the system losses and volume/weight. These improvements mainly originate from the replacement of high-voltage transistors, typical of two-level converters, with low-voltage, e.g., 200 V, devices, offering superior electric performance. Hence, two low on-state resistance silicon (Si) and gallium nitride (GaN) 200 V power semiconductors are comprehensively characterized in this article to support the multi-objective optimization and the design of M/ML power converters. First, the selected devices are analyzed experimentally determining their conduction, thermal, and switching characteristics; for this purpose, a novel ultra-fast transient calorimetric measurement method is introduced and explained in detail. In the course of this analysis, an unexpected switching loss mechanism is observed in the Si devices at hand; the physical reason of this behavior is clarified and it is proven to be solved in the next-generation research samples, which are also characterized by measurements. Finally, the influence of the measured power semiconductors’ performance on the overall efficiency and power density of a typical converter is determined through a case study analyzing a hard switching half-bridge operated as a single-phase inverter, i.e., the fundamental building block of several M/ML topologies. It is concluded that, in this voltage and power class, GaN e-FETs are nowadays approximately a factor of three superior to Si power MOSFETs; however, the better heat dissipation achieved by the latter still makes them the preferred solution for higher power applications.

Mathematical model of the architecture of a distributed information-measuring system based on cloud and fog technologies

This article describes the formulation of a mathematical model for optimizing the structure of a distributed information-measuring system based on a multi-level topology. The paradigm of cloud, fog and boundary computing is used, which allows building a modern network infrastructure within the framework of the industrial IoT concept. The most typical example of the use of this paradigm may be intelligent power supply networks and distributed systems for monitoring the transportation of gas or oil products. To solve the problem, it is proposed to use an approach based on a genetic algorithm.

A Modular Design Approach to Provide Exhaustive Carrier-Based PWM Patterns for Multilevel ANPC Converters

The number of applicable carrier-based pulsewidth modulation (PWM) patterns increases with the growth of output levels in scalable multilevel topologies, such as active-neutral-point-clamped (ANPC) converters. Therefore, it is hard to optimize PWM for such topology, especially with large output levels. In this paper, a simplified and modular carrier-based PWM design approach for multilevel ANPC converters is proposed. Inspired by the decomposition theory, the topology decomposition is introduced in this paper to decompose an N -level ANPC converter into low-level subtopologies. Then, the complete set of applicable PWM patterns is derived based on ANPC operation principles, which makes it possible to optimize the performance based on the various requirements in applications. Meanwhile, the carrier-based PWM is implemented through the utilization of subtopologies with low-level modulation schemes, such that the design process of carrier-based PWM is greatly simplified and modularly realized. Both the complete PWM patterns and PWM design examples with experimental results of several ANPC converters are provided to show the feasibility and modularity of the proposed method.

Comparison of Inverter Topologies by Total Har-Monic Distortion of Output Voltage

This paper is devoted to comparison analysis of different topologies of the inverters that are used in the systems with alternative energy sources. A brief theoretical review of the most commonly used topologies for the power systems with alternative energy sources are given, their main advantages and disadvantages are determined. In close details were considered principles of construction and operation of the topology with impedance input circuit (z-inverter), and topology with quasi-impedance input circuit (quasi-z-inverter). A special feature of these topologies is ability to operate in special mode which is called “shoot-trough state”. It means that one of the inverter’s arms is short-circuited for a small period of time which substitutes a part of the zero state. Possibility to operate in such state allows to increase the input voltage of the inverter that can be very suitable in inverters that are included in photovoltaic power systems. Implementation of shoot-trough state allows tracking maximum power point of the photovoltaic array without implementation of additional converters for this. Implementation of quasi-z-topology allows to reduce the load on the passive components of the impedance circuit and to ensure continuous power take-off from the solar batteries array, which makes it easier to track the maximum power point. As an evolution of the cascade multilevel and z- / quasi-z-inverter topologies multilevel cascaded topologies with z- and quasi-z-inverters in separate blocks were considered. The main principles of this structure allows to unite all advantages of cascaded multilevel and z-/quasi-z topologies in one device but also bring few drawbacks such as complexity of the implementation and higher cost of the resulting device. These topologies were simulated in Matlab Simulink, output voltage spectra and total harmonic distortion was obtained and analyzed. According to the obtained results of the simulation and review recommendations for proper selection of the topology of inverter depending on the type and sensitivity to the quality of the input voltage of the load and type of chosen alternative energy source are given. According to this results convenient cascaded multilevel topology could be recommended for the loads that are especially vulnerable to low quality of input supply voltage such as analog amplifiers and radio receivers as topology that have lowest THD (Total harmonic distortion) ratio. Z-/quasi-z-topologies are appropriate to consider as a converter of photovoltaic power system that will work on loads that are not demanding to the quality of supply voltage as topologies with highest level of THD of the output voltage. Cascaded topologies with z- and quasi-z-inverters in separate blocks could be considered as a compromise that could be used in photovoltaic power systems that works on vulnerable loads but such solution increases the cost of a whole power system and complication of the control system.

Increasing the quality and power capacity of HERIC PV-Inverter through multilevel topology implementation

In photovoltaic generation applications, high efficiency and good output power quality inverter are very important. The most common way to improve the quality of the inverter output voltage is to increase the switching frequency. However, at the same time, this method will increase power losses. This paper introduces a new topology inverter: HERIC multilevel, as an inverter that has good voltage quality (low THD) with a low switching frequency. This topology was tested and analyzed by performing simulations to compare it with the conventional HERIC and cascaded H-Bridge inverters. The results prove that the multilevel HERIC inverter has a lower THD compared to the two inverters. At the switching frequency of 2500Hz; Multilevel HERIC inverters have THD, 1.23%, cascaded H-bridge has 1.34% THD, and conventional HERIC THD 11.4%.

An Active Capacitor Voltage Balancing Method for Seven-Level Hybrid Clamped (7L-HC) Converter in Motor Drives

Multilevel converters are widely applied in medium voltage (MV) drive systems due to the attractive features, such as the ability to use devices with lower voltage ratings, high equivalent switching frequency, etc. Recently, a multilevel topology, named seven-level hybrid clamped (7L-HC), is proposed for MV drives. It has a competitive number of devices, showing the potential to build low-cost 7L converters. However, to ensure the wide frequency range operation and power quality of MV drives, its dc-link capacitors and floating capacitors must be controlled properly with balanced voltages. In this paper, an active voltage balancing method is proposed for the 7L-HC converter. This method can effectively balance all the capacitor voltages under a wide frequency range. The method is embedded in the PWM procedure without modifying the control strategies. Simulation and experimental results are provided to validate the proposed method.

Single‐phase Modified T‐type–based multilevel inverter with reduced number of power electronic devices

In this research work, a generalized structure of multilevel topology is proposed that can be extended by cascading the modules. Proposed modular topology is modified T-type structure that requires comparative reduced number of power components than other existing structures of multilevel inverter. Each module encompasses of three DC sources and 10 power switches. Both positive and negative voltage levels can be generated without the use of H-bridge inverter; thus, lower voltage rating power switches are employed for proposed modular topology. To generate the output voltage levels, the nearest level control is implemented on the experimental setup using dSPACE 1103 controller. To verify the performance of the proposed inverter, experimental validation of various topologies based on different algorithms is performed to generate 15-level, 17-level, 27-level, and 31-level at different load conditions. Moreover, different state-of-art topologies are compared with proposed topology in terms of the required number of voltage levels, DC sources, power switches, driver circuits, and total standing voltage.

Starting torque and torque ripple reduction using SVPWM based vector control of induction motor with nine-level cascaded multilevel inverter fed with solar PV power

This paper is an attempt to develop an Induction Motor Drive System with Multilevel Inverter topology for reduced torque ripple application. A Nine level-cascaded multilevel inverter is developed for the induction motor drive with SVPWM control powered by boost converter fed using solar PV supply. The SVPWM control based implementation of vector control using a multilevel inverter topology needs a multilevel SVPWM control technique, which is implemented in this paper. The Solar power supplied is applied with the MPPT technique and the supplied DC power is fed to the three phase cascaded 9 level multilevel inverter. The vector control of induction motor is carried out using the SVPWM technique on the multilevel topology. The torque ripple reduction in the output is observed and compared with the vector control of induction motor. Matlab based implementation is carried out and the results are tabulated and inferred.

An adaptable different-levels cascaded h-bridge inverter analysis for PV grid-connected systems

&lt;span&gt;Multi-level inverters (MLIs), have gained popularity in the last few years as a result of their low total harmonic distortions (THD) as well as their output waveform which is of high quality. The converter which considers more appropriate for applications of photovoltaic (PV)beyond the varying MLIs arrangementsis the Cascaded H-Bridge-(CHB) (MLI), meanwhile each PV panel may be served as an independent DC supply for any CHB unit&lt;span style="text-decoration: underline;"&gt;.&lt;/span&gt; Through the use of MATLAB/Simulink, the efficiency of symmetrical single phase MLI in terms of the number of switches, harmonic content in addition to the stresses of voltage through theswitches that exist at photovoltaic cell by means of input source is enhanced; varying parameters like output current, voltage and power, and THD at 5-level 7-level and 9-level Cascaded MLI are observed. In this paper, attention is paid to a multi-level topologies which is flexible and based on cascaded MLI intended for PV grids connected system. An observation of the output voltage becomes closer to the sine wave as the levels increase, while the increase in the levels of Cascaded Multilevel Inverter causes the total harmonic distortion to decrease.&lt;/span&gt;

Analysis and Design of a High Power Density Flying-Capacitor Multilevel Boost Converter for High Step-Up Conversion

This paper explores the use of the flying-capacitor multilevel (FCML) topology in high step-up conversion. Compared to the conventional two-level boost converter, the FCML topology utilizes high energy density capacitors to facilitate inductors with storing and transferring energy during the conversion process, which brings features, such as lower voltage stress on the switches, reduced voltage stress on the inductor, and high effective switching frequency at the switching node. As a result, the total volume of the passive components in the converter is greatly reduced while maintaining high efficiency at high voltage gain. To demonstrate the potential high power density and high efficiency, a hardware prototype that converts 100 V to 1 kV with 820-W maximum output power is built. Such specifications require careful optimizations in many aspects of the converter to ensure a high power density and efficiency design. The implemented solutions and associate design process are presented in detail, with comparison with other state-of-the-art solutions. The hardware prototype has successfully demonstrated a peak efficiency of 94.1%, and 329 W/in $^3$ (20 W/cm $^3$ ) overall power density.

An Isolated Multilevel Quasi-Resonant Multiphase Single-Stage Topology for 380-V VRM Applications

In order to increase the efficiency of modern microprocessor power supplies used in data centers, 380-V dc power distribution systems have been attracting attention due to their high efficiency and high reliability. This paper presents an innovative single-stage approach for 380-V voltage regulator modules (VRMs) based on a quasi-resonant multilevel topology constant on -time operation. The proposed topology inherently integrates the multiphase approach, providing fast phase shedding and flat high-efficiency curves even at light-load conditions. This is a unique advantage, which is not possible to establish in the two-stage approach, which is very important in server architectures, and where high efficiency is required even at light-load conditions. This paper analyzes the circuit topology and proposes a control architecture for fast transient response, including current-sharing capabilities. The digital controller has been implemented in 0.16- $\mu$ m lithography together with a digital pulsewidth modulation with a 195-ps resolution and a 40-MS/s 7-bit analog-to-digital converter. Experimental results show an efficiency of 93% for a 120-A 380–1.8-V VRM power supply.