Multi-level NAND Flash Memory Research Articles

Enhancing Data Storage Reliability and Error Correction in Multilevel NOR and NAND Flash Memories through Optimal Design of BCH Codes

Enhancing Data Storage Reliability and Error Correction in Multilevel NOR and NAND Flash Memories through Optimal Design of BCH Codes

Performance Analysis of Concatenated Coding to Increase the Endurance of Multilevel NAND Flash Memory

The increasing storage density of modern NAND flash memory chips, achieved both due to scaling down the cell size, and due to the increasing number of used cell states, leads to a decrease in data storage reliability, namely, error probability, endurance (number of P/E cycling) and retention time. Error correction codes are often used to improve the reliability of data storage in multilevel flash memory. The effectiveness of using error correction codes is largely determined by the model accuracy that exhibits the basic processes associated with writing and reading data. The paper describes the main sources of disturbances for a flash cell that affect the threshold voltage of the cell in NAND flash memory, and represents an explicit form of the threshold voltage distribution. As an approximation of the obtained threshold voltage distribution, a Normal-Laplace mixture model was shown to be a good fit in multilevel flash memories for a large number of rewriting cycles. For this model, a performance analysis of the concatenated coding scheme with an outer Reed-Solomon code and an inner multilevel code consisting of binary component codes is carried out. The performed analysis makes it possible to obtain tradeoffs between the error probability, storage density, and the number of P/E cycling. The resulting tradeoffs show that the considered concatenated coding schemes allow, due to a very slight decrease in the storage density, to increase the number of P/E cycling up to 2–2.5 times than their nominal endurance specification while maintaining the required value of the bit error probability.

A shared page-aware machine learning assisted method for predicting and improving multi-level cell NAND flash memory life expectancy

NAND flash memory is widely used in consumer electronics, personal computers, and enterprise data storage servers. The most prevalent source of flash memory errors is retention errors, which are mainly caused by leakage of charges. It has been observed that inside the chip, some flash memory blocks exhibit greater endurance to the retention errors than others. In an effort to prolong life expectancy, previous studies focus on improving the Raw Bit Error Rate (RBER) metric at page and block levels, without due consideration of the geometry of shared pages. In this paper, the first insight we provide is that groups of shared pages have different RBER values, and should be analyzed separately. We use this insight to construct a machine learning model to predict the blocks which have less endurance, using the characterization data of new unused flash memory chip(s). This is accomplished by extracting location-sensitive and value-sensitive features from the shared pages group, and engineering them into more sophisticated and explainable features. Furthermore, we describe how our proposed prediction model can be used in combination with the existing flash translation layer (FTL) wear-leveling algorithm to increase lifetime. We evaluated the proposed prediction and lifetime improvement method for four different machine learning techniques, among which Support Vector Machine (SVM) achieved superior accuracy up to 85% at a lower computational overhead.

Implementation of Data Search in Multi-Level NAND Flash Memory by Complementary Storage Scheme

We develop a novel scheme to realize data search in NAND flash memories, which is important for a wide variety of applications in data centers. In our design, the pair unit consists of double neighbor cells in the NAND string, one “data cell” and one “complementary cell”. The NAND string will be at the “Pass” state only when the searching data are completely matched with the stored data. Parameters that affect data search performance are analyzed systematically. Based on simulations in vertically stacked 3D NAND structures, it is shown that the bit-line current ratio of the fully matched case to the worst case of one mismatched data is more than ~104 in both MLC (multi-level cell) and TLC (triple-level cell) modes, and ~102 can still be obtained in QLC (quad-level cell) mode after read voltage optimizations. These results indicate that the proposed scheme is effective for data search in multi-level NAND flash memories and also friendly for peripheral circuits design.

Low Read Latency Rewriting Codes for Multi-Level 3-D NAND Flash

Rewriting codes can improve the lifetime capacity of NAND flash. All existing $q$ -ary rewriting codes for NAND flash assume that the exact cell levels are known to decoders, and thus the number of reads needed is $q-1$ , while the current NAND technology enables low latency page reads by dividing a physical page into $\log q$ logical pages, so that the average number of reads per page is $\frac {q-1}{\log q}$ . We consider 2-write rewriting codes that enable low latency page reads for multi-level NAND flash memories. We design a low read latency rewriting code that enables 17% capacity improvement and maintains 1.5 reads per page for four-level multiple-level cells. We also design codes for eight-level triple level cells that enable 11% and 24% capacity improvement with 2 and 2.5 reads per page, respectively. The same Gray codes in current NAND technology that map binary data to physical cell levels are applied to avoid redesigning hardware and circuits inside the chip.

Capacity of Multilevel NAND Flash Memory Channels

In this paper, we initiate a first information-theoretic study on multilevel NAND flash memory channels with intercell interference. More specifically, for a multilevel NAND flash memory channel under mild assumptions, we first prove that such a channel is indecomposable and it features asymptotic equipartition property; we then further prove that stationary processes achieve its information capacity, and consequently, as the order tends to infinity, its Markov capacity converges to its information capacity; eventually, we establish that its operational capacity is equal to its information capacity. Our results suggest that it is highly plausible to apply the ideas and techniques in the computation of the capacity of finite-state channels, which are relatively better explored, to that of the capacity of multilevel NAND flash memory channels.

Dummy Read Scheme for Lifetime Improvement of MLC NAND Flash Memories

Program/erase cycling endurance is one of the most critical reliability challenges for multi-level NAND flash memories. Deliberately designed delay between cycles is found to extend the endurance of nanoscale NAND flash memory cells. In addition, the effect of chip temperature is extensively investigated. A new dummy read operation scheme is proposed to further enhance cell reliability by effectively suppressing cycling-induced error bits in gigabit memory arrays.

Detector for MLC NAND Flash Memory Using Neighbor-<italic>A-Priori</italic> Information

Cell-to-cell interference (CCI), arising from parasitic coupling-capacitance between adjacent cells, is a major factor for the degradation of cell threshold voltage in today’s flash memory chips. In this paper, three novel postprocessing detection schemes that exploit the a priori information of neighboring/interfering cells for mitigating the CCI effect in multilevel cell NAND flash memory are presented. The proposed schemes are referred to as the Even- A-Priori (Even-AP), the All- A-Priori (All-AP), and the All-AP-coupling-capacitance ratio (CCR) detectors. The main idea is to remove the CCI component from the interfering cells before CCI cancellation from the victim cell. Specifically, the mean CCRs along the victim cell’s vertical and diagonal directions are estimated to enable more accurate CCI cancellation. Performance analysis and simulation results show that the channel signal-to-noise ratio performance can be improved by up to 2 dB at a cell storage capacity of 1.8 bits/cell, which is significantly improved compared with some prior-art detection schemes.

Implications of the Logical Decode on the Radiation Response of a Multi-Level Cell NAND Flash Memory

The radiation response of a multi-level cell (MLC) NAND flash is used to determine the organization of logical states as they correspond to floating gate charge levels of constituent bit cell transistors. This “logical decode” is then used to demonstrate how an MLC device can be used to emulate a single-level cell (SLC) flash with total dose radiation sensitivity equivalent to and even surpassing that of a comparable actual SLC device. In addition, it is shown that the logical decode must be taken into account when performing radiation testing on MLC flash devices so as to gather accurate worst case response data.

Single and Multiple Cell Upsets in 25-nm NAND Flash Memories

We analyzed floating-gate upsets in 25-nm multilevel cell NAND Flash memories irradiated with heavy ions, including alpha particles. Compared to multilevel cell memories of previous generations, these devices show no apparent error dependence on the program level, adherence to the cosine law, and a large number of multiple cell upsets (MCUs). Floating-gate errors were mapped to their physical location, and MCUs were studied as a function of their multiplicity, direction, particle linear energy transfer, irradiation angle, and program level.

멀티 레벨 낸드 플레쉬 메모리에서 주변 셀 상태에 따른 데이터 유지 특성에 대한 연구

멀티 레벨 낸드 플레쉬 메모리에서 주위 셀의 문턱 전압상태에 따른 데이터 유지 특성을 연구하였다. 열을 가해 셀의 데이터 보전특성을 판정하는 열적 열하 특성에서 주목하는 셀의 문턱 전압이 변화하는데 문턱전압의 변화는 선택된 셀 주위에 있는 셀들이 가장 낮은 문턱 전압 상태로 있는 셀들의 수가 많을수록 커진다. 그 이유는 전하의 손실이 이루어지는 낸드 플레쉬셀의 본질적인 특성 뿐 아니라, 주위 셀 사이의 측면 전계 때문이다. 전계에 대한 모사 결과로부터 전계의 증가 현상을 발견할 수 있고, 이로 인한 전하의 손실이 소자 스케일 다운에 따라 더 증가함을 알 수 있다.

Guest Editors’ Introduction to Special Issue on Advances in DSP System Design

The constant advances in IC technologies have introduced new challenges for implementations and design methodologies; higher integration level allows more complex systems to be implemented but on the other hand implementations often have strict constraints on power consumption. These challenges are present in signal processing systems implying the need to improve design methods and find more efficient algorithm-architecture optimizations. This special issue contains a selection of recent papers on design and implementation of signal processing systems ranging from circuit level architectures to scheduling methods and from application-specific architectures to implementations on many-core systems. In Data Center Switch for Load Balanced Fat-Trees, Lai, and Chiu demonstrate a fault tolerant switch IC operating at the maximum rate of 5.8 Gbps per channel. This work employs a load-balanced fat-tree architecture that does not consume all of its bandwidth even under heavy traffic. When there are broken links or faulty switches in the network even in heavy traffic load situations, available bandwidth remains in every connection pattern and alternative paths are provided to re-route the traffic. Fault tolerance capability evaluations of link or switch faults in the fattree network are given to support the presented idea, and a 4×4 Banyan type switch IC is developed as the commodity switch for building the fault tolerant fat-tree data center networks. Lee and Sung propose a cell-to-cell interference (CCI) cancellation technique for multi-level NAND flash memory in their paper Least Squares Based Coupling Cancellation for MLC NAND Flash Memory with a Small Number of Voltage Sensing Operations. Their two-step algorithm consists of training and then interference removal performed during the page read operation. A least-squares adaptive CCI canceller is developed and optimal quantization schemes are studied. Experimental results show a significant BER improvement despite a low number of voltage sensing operations. In A Fast Recursive Algorithm and Architecture for Pruned Bit-Reversal Interleavers, Mansour describes an algorithm and architecture for implementing interleavers used in communications applications such as errorcorrecting codes (turbo codes) and bit-interleaved coded modulation. A mathematical formulation for developing flexible-length interleavers is developed along with a study of permutation statistics. Practical examples of implementations of parallel interleavers are provided. In Highly Parallelable Bidimensional Median Filter for Modern Parallel Programming Models, Sanchez and Rodriguez present efficient parallel implementation methods for median filtering. The authors implement their previous work on the parallel ccdf-based median filter (PCMF) on a GPU (Graphics Processing Unit), and show that the proposed median filtering algorithm is efficient and can outperform other generic median filters for the GPU. The proposed algorithm is implemented in three parallel programming models: SIMD Intel, multi-core Intel with SIMD, and SIMT (CUDA). Additionally they make use of the salt & pepper noise model to improve the image reconstruction quality with a small performance impact. J. Takala (*) Department of Pervasive Computing, Tampere University of Technology, Tampere, Finland e-mail: jarmo.takala@tut.fi

Low-energy error correction of NAND Flash memory through soft-decision decoding

The raw bit error rate of NAND Flash memory increases as the semiconductor geometry shrinks for high density, which makes it very necessary to employ a very strong error correction circuit. The soft-decision-based error correction algorithms, such as low-density parity-check (LDPC) codes, can enhance the error correction capability without increasing the number of parity bits. However, soft-decision error correction schemes need multiple precision data, which obviously increases the energy consumption in NAND Flash memory for more sensing operations as well as more data output. We examine the energy consumption of a NAND Flash memory system with an LDPC code-based soft-decision error correction algorithm. The energy consumed at multiple-precision NAND Flash memory as well as the LDPC decoder is considered. The output precision employed is 1.0, 1.4, 1.7, and 2.0 bits per data. In addition, we also propose an LDPC decoder-assisted precision selection method that needs virtually no overhead. The experiment was conducted with 32-nm 128-Gbit 2-bit multi-level cell NAND Flash memory and a 65-nm LDPC decoding VLSI.

Linking EUV lithography line edge roughness and 16nm NAND memory performance

Resist roughness is one of the effects of process uncertainties in extreme UV lithography. All the lithographic elements, such as source, mask, optical system, resist and metrology, contribute to line roughness. As a result, line edge roughness is still a challenge to be tackled for 22 and 16nm transistor devices. In this paper, the impact of post-litho smoothing processes such as ion-beam implant and plasma etch treatment on state-of-the-art extreme UV lithography is reported. Top-down and cross section electron microscopy were used to evaluate low and high frequency components of line edge roughness by means of power spectral density analysis. To compute roughness impact on bit error rate performance of floating gate devices, line edge profiles were first rebuilt, and then injected into a Monte Carlo variability aware simulator for electrical evaluation of a 16nm multi-level NAND Flash memory array. Electrical variability simulations based on actual experimental roughness profiles were executed to quantify the impact of line edge roughness on the device reliability. It was found that inter-transistor low frequency roughness impacts the memory performance with a failure factor 3-5 times higher compared to the same electrical model without considering any stochastic variation. Intra-transistor high frequency roughness showed only a marginal effect compared inter-transistor variations. Moreover, it was demonstrated that the bit error rate exponentially depend on resist line edge roughness. Finally, by combining both experimental analysis and electrical assessment, it was possible to quantify the contribution of post-litho smoothing processes on the error correction code performance for such memory devices.

Evaluation of Mechanisms in TID Degradation and SEE Susceptibility of Single- and Multi-Level High Density NAND Flash Memories

Heavy ion single-event measurements and total ionizing dose (TID) response for 8 Gb commercial NAND flash memories are reported. Radiation results of multi-level flash technology are compared with results from single-level flash technology. The single-level devices are less sensitive to single event upsets (SEUs) than multi-level devices. In general, these commercial high density memories exhibit less TID degradation compared to older generations of flash memories.

High-Speed Multilevel nand Flash Memory With Tight $V_{\rm th}$ Distribution Using an Engineered Potential Well and Forward-Bias Adjusted Programming

This paper reports a high-speed multilevel-cell nand Flash memory device using a Si- SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -TiN- TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -TaN (SOTTOT) engineered potential well (EW). The SOTTOT EW Flash memory device has very fast cell programming speed and good data retention. A 16-kbit nand memory block using SOTTOT cells was programmed using a forward-bias-adjusted programming scheme, which enables bit adjustability during page programming to suppress the development of fast bits. The SOTTOT memory block shows fast programming speed (~40 μs/page), tight threshold voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) distribution (~0.22 V/level), and clear <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> -level margins (~0.9 V) for the eight-level programming. The SOTTOT memory block also shows good resistance against pass/read disturbances as well as good ten-year data retention at an ambient temperature of 75 °C throughout 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> programming/erasing cycling.

Multilevel Charge Storage in a Multiple Alloy Nanodot Memory

A multilevel charge storage in a multiple FePt alloy nanodot memory is investigated for the first time. It is demonstrated that the memory structure with multiple FePt nanodot layers effectively realizes a multilevel state by the adjustment of gate voltage. Metal oxide semiconductor (MOS) capacitors with four FePt nanodot layers as a floating gate are fabricated to evaluate the multilevel cell characteristic and reliability. Here, the effect of memory window for a nanodot diameter is also investigated, and it is found that a smaller dot size gives a larger window. From the results showing good endurance and retention characteristics for the multilevel states, it is expected that a multiple FePt nanodot memory using Fowler–Nordheim (FN) tunneling can be a candidate structure for the future multilevel NAND flash memory.

A Novel Sensing Scheme for Reliable Read Operation of Ultrathin-Body Vertical nand Flash Memory Devices

In this brief, an advanced sensing scheme for ultrathin-body vertical Flash memory device is introduced experimentally. Without an increment in the number of read operations, the program/erase states of a memory cell can be identified exactly even with the existence of electrical interference between cells having an ultrathin vertical channel in common. The novel sensing scheme, i.e., the double sensing per 2 bits method, was validated for a fabricated device with a channel thickness of 80 nm. The proposed method can be also used as reference for establishing a smart sensing scheme for multilevel cell NAND Flash memory devices.

Floating-Gate Coupling Canceller for Multi-Level Cell NAND Flash

Floating-gate coupling occurs due to voltage changes in neighboring floating-gates. Coupling noise is difficult to overcome because of its non-linear property. We propose a coupling canceller for cancelling the coupling effect in multi-level cell NAND flash memory, and compare its performance with threshold detection. Simulation results show that the proposed floating-gate coupling canceller is an effective scheme for suppressing coupling noise.

Improving Read Disturb Characteristics by Self-Boosting Read Scheme for Multilevel NAND Flash Memories

A new NAND string and its read operation scheme using self-boosting as a solution for improving read disturb characteristics of NAND flash memories are proposed. By using the proposed self-boosting read scheme, which includes an optimized bias voltage and adjusted threshold voltage (Vth) of dummy cells, the self-boosted channel voltage prevents soft-programming in unselected memory cells during read operation due to reduced electric field across tunnel oxide. Compared to the conventional scheme this leads to a significant improvement in read disturb characteristics. From simulation and measurement results, the worst electric field of the proposed NAND flash memory during read operation is decreased by around 50% and Vth shifts caused by read disturb is lowered by around 40%, compared to conventional NAND. The proposed NAND was fabricated in a 60 nm NAND technology and successfully demonstrated.