Low Read Latency Rewriting Codes for Multi-Level 3-D NAND Flash

Abstract

Rewriting codes can improve the lifetime capacity of NAND flash. All existing $q$ -ary rewriting codes for NAND flash assume that the exact cell levels are known to decoders, and thus the number of reads needed is $q-1$ , while the current NAND technology enables low latency page reads by dividing a physical page into $\log q$ logical pages, so that the average number of reads per page is $\frac {q-1}{\log q}$ . We consider 2-write rewriting codes that enable low latency page reads for multi-level NAND flash memories. We design a low read latency rewriting code that enables 17% capacity improvement and maintains 1.5 reads per page for four-level multiple-level cells. We also design codes for eight-level triple level cells that enable 11% and 24% capacity improvement with 2 and 2.5 reads per page, respectively. The same Gray codes in current NAND technology that map binary data to physical cell levels are applied to avoid redesigning hardware and circuits inside the chip.