Multi-level Memory Cell Research Articles

High performance low power multilevel oxide based RRAM devices based on TiOxNy/Ga2O3 hybrid structure

In this study, the resistive memory devices with Ag/TiOxNy/Pt structure and Ag/TiOxNy/Ga2O3/Pt structure are fabricated. The results showed that they exhibit typical resistive behaviors as well as excellent cycling and retention characteristics (>104 s). Especially, the double-layer device with Ga2O3 layer exhibits superior resistive behavior, which has a larger storage window (ON/OFF ratio >105), a smaller set voltage (0.17 V) and a reset voltage (−0.057 V), and lower power consumption (21.7, 0.17 μW) compared with the single-layer device. Furthermore, the Ag/TiOxNy/Ga2O3/Pt device demonstrates ultraviolet light (UV-365 nm)-dependent resistance state (RS), which is advantageous for multilevel memory cells. As the intensity of UV light increases, eight high resistance state (HRS) levels are produced. Finally, the conductive mechanism for both device structures is discussed, and it is found that the conductive filaments mechanism dominates in the low resistance state. However, for the HRS, the single-layer TiOxNy device is dominated by the space charge-limited conduction mechanism, and the double-layer TiOxNy/Ga2O3 device is dominated by the Schottky emission mechanism.

Drift of Schottky Barrier Height in Phase Change Materials.

Phase-change memory (PCM) devices have great potential as multilevel memory cells and artificial synapses for neuromorphic computing hardware. However, their practical use is hampered by resistance drift, a phenomenon commonly attributed to structural relaxation or electronic mechanisms primarily in the context of bulk effects. In this study, we reevaluate the electrical manifestation of resistance drift in sub-100 nm Ge2Sb2Te5 (GST) PCM devices, focusing on the contributions of bulk vs interface effects. We employ a combination of measurement techniques to elucidate the current transport mechanism and the electrical manifestation of resistance drift. Our steady-state temperature-dependent measurements reveal that resistance in these devices is predominantly influenced by their electrical contacts, with conduction occurring through thermionic emission (Schottky) at the contacts. Additionally, temporal current-voltage characterization allows us to link the resistance drift to a time-dependent increase in the Schottky barrier height. These findings provide valuable insights, pinpointing the primary contributor to resistance drift in PCM devices: the Schottky barrier height for hole injection at the interface. This underscores the significance of contacts (interface) in the electrical manifestation of drift in PCM devices.

Multilevel thermal memory cell based on cyclic temperature experiment under glassy phase of frustrated magnet

We depict here that the value of the relaxed magnetization follows a unique path for each temperature below the phase transition temperature () for pristine and its substituents. Here we propose a way to access these paths by cyclic thermal manipulations. Thus the magnetization corresponding to each temperature below can be utilized in multilevel data storage that has a potential application in the thermal memory cell. Furthermore, these results were compared with another route used in the thermal memory cell and were proven more efficient and faster than the latter one.

Synaptic array using multi-level AND flash memory cells for hardware-based neural networks

We propose an AND array architecture in which bit-lines (BLs) and source-lines (SLs) of thin film transistor (TFT)-type flash memory cells used as synapses are arranged in parallel, and show the fabricated device and array characteristics. A top gate dielectric stack and a bottom gate dielectric stack serve to store a synaptic weight and select excitatory or inhibitory synapses, respectively. Multi-level (>5-bit) synaptic weight states and selective write operations in the AND array architecture are achieved by utilizing a simple update pulse scheme. Furthermore, weighted sum operation in a fabricated 9 × 3 AND flash synaptic array is successfully carried out by measuring BL currents when input pulses are applied to multiple word-lines (WLs) for hardware-based neural networks (HNNs).

A novel ferroelectric nanopillar multi-level cell memory

In this work, we present a novel multi-level non-volatile memory (NVM) device where ferroelectric (FE) nanopillars are embedded in a dielectric (DE) medium. Using our in-house 3D phase field simulator developed to treat the FE–DE composite system stably, we demonstrate that n FE nanopillars can generate more than 2n states, enabling high storage capacity. The multistates of the pillar array device are attributed to the depolarization field modulation with the pillar height and the multi-domain topological states of nanoscale FE structures.

Data Representation Aware of Damage to Extend the Lifetime of MLC NAND Flash Memory

Multilevel cell (MLC) NAND flash memory uses the voltages of the memory cells to represent bits, but high voltages cause much more damage on the cells than low voltages. Free space in MLC can be leveraged to reduce the usage of the high voltages and thus extend the lifetime of MLC. However, limited by the conventional data representation rule that represents bits by the voltage of one single cell, the high voltages are used in a high probability. To fully explore the potential of the free space on reducing the usage of high voltages without changing the total density of MLC, we propose a novel data representation aware of damage, named DREAM. DREAM uses the low voltage combinations of multiple cells instead of the voltage of one single cell to represent bits. It enables to represent the same bits through flexibly replacing the high voltages in some cells with the low voltages in other cells when free space is available. Hence, high voltages which cause more damage are less used and the lifetime of the MLC memory is extended. In addition, complementary techniques are proposed to mitigate performance loss induced by DREAM. Theoretical analysis and simulation results demonstrate the effectiveness and efficiency of DREAM.

Overcoming bit loss mechanism in self‐amplified multilevel silicon‐oxide‐nitride‐oxide‐silicon memory cell

AbstractThis work reports on the triple‐level NAND flash cell realized from self‐amplified (SA) double gate (DG) tunneling‐based silicon‐oxide‐nitride‐oxide‐silicon (T‐SONOS) memory device. Through calibrated simulations, we show that capacitive coupling between the front gate and back gate can be used to store eight states (or 3 bits), that is, from “000” to “111,” in a T‐SONOS memory device with the readable difference between each level at lower programming voltages. The performance of the multilevel T‐SONOS cell is compared with the inversion mode SONOS (I‐SONOS) multilevel cell. Results highlight that gate length (Lg) scaling from 100 to 25 nm significantly deteriorates the threshold voltage associated with the lower states in the I‐SONOS multilevel cell. However, highly stable eight states can be achieved in a multi‐level T‐SONOS cell at Lg = 25 nm. The results highlight the potential of SA T‐SONOS cell for designing multilevel memory cell arrays.

Toward Highly Robust Nonvolatile Multilevel Memory by Fine Tuning of the Nanostructural Crystalline Solid-State Order.

Organic resistive memory (ORM) offers great promise for next-generation high-density multilevel-cell (MLC) data storage. However, the fine tuning of crystalline order among its active layer still remains challenging, which largely restricts ORM behavior. Here, an exceptional solid-state transition from disordered orientations to highly-uniform orientation within the ORM layer is facilely triggered via molecular strategic tailoring. Two diketopyrrolopyrrole-based small molecular analogues (NI1 TDPP and NI2 TDPP) are demonstrated to display different symmetry. The asymmetric NI1 TDPP shows an irregular solid-state texture, while the centro-symmetric NI2 TDPP conforms to an ordered out-of-plane single-crystalline pattern that aligns with the foremost charge transportation along the substrate normal, and exhibits excellent MLC memory characteristics. Moreover, this highly oriented pattern guarantees the large-area film uniformity, leading to the twofold increase in the yield of as-fabricated ORM devices. This study reveals that the solid-state crystalline nanostructural order of organic materials can be controlled by reasonable molecular design to actuate high-performance organic electronic circuits.

Ratio-based multi-level resistive memory cells

Ratio-based encoding has recently been proposed for single-level resistive memory cells, in which the resistance ratio of a pair of resistance-switching devices, rather than the resistance of a single device (i.e. resistance-based encoding), is used for encoding single-bit information, which significantly reduces the bit error probability. Generalizing this concept for multi-level cells, we propose a ratio-based information encoding mechanism and demonstrate its advantages over the resistance-based encoding for designing multi-level memory systems. We derive a closed-form expression for the bit error probability of ratio-based and resistance-based encodings as a function of the number of levels of the memory cell, the variance of the distribution of the resistive states, and the ON/OFF ratio of the resistive device, from which we prove that for a multi-level memory system using resistance-based encoding with bit error probability x, its corresponding bit error probability using ratio-based encoding will be reduced to x^2 at the best case and x^{sqrt{2}} at the worst case. We experimentally validated these findings on multiple resistance-switching devices and show that, compared to the resistance-based encoding on the same resistive devices, our approach achieves up to 3 orders of magnitude lower bit error probability, or alternatively it could reduce the cell’s programming time and programming energy by up 5–10times, while achieving the same bit error probability.

High-bandwidth light inputting multilevel photoelectric memory based on thin-film transistor with a floating gate of CsPbBr3/CsPbI3 blend quantum dots

The electronic-photonic convergent systems can overcome the data transmission bottleneck for microchips by enabling processor and memory chips with high-bandwidth optical input/output. However, current silicon-based electronic-photonic systems require various functional devices/components to convert high-bandwidth optical signals into electrical ones, thus making further integrations of sophisticated systems rather difficult. Here, we demonstrate thin-film transistor-based photoelectric memories employing CsPbBr3/CsPbI3 blend perovskite quantum dots (PQDs) as a floating gate, and multilevel memory cells are achieved under programming and erasing modes, respectively, by imputing high-bandwidth optical signals. For different bandwidth light input (i.e. 500–550, 575–650 and 675–750 nm) with the same intensity, three levels of programming window (i.e. 3.7, 1.9 and 0.8 V) and erasing window (i.e. −1.9, −0.6 and −0.1 V) are obtained under electrical pulses, respectively. This is because the blend PQDs have two different bandgaps, and different amounts of photo-generated carriers can be produced for different wavelength optical inputs. It is noticed that the 675–750 nm light inputs have no effects on both programming and erasing windows because of no photo-carriers generation. Four memory states are demonstrated, showing enough large gaps (1.12–5.61 V) between each other, good data retention and programming/erasing endurance. By inputting different optical signals, different memory states can be switched easily. Therefore, this work directly demonstrates high-bandwidth light inputting multilevel memory cells for novel electronic-photonic systems.

Multi-Level Memory Comprising Low-Temperature Poly-Silicon and Oxide TFTs

In this letter, a new multi-level memory cell using low-temperature polycrystalline silicon and oxide (LTPO) thin-film transistor (TFT) backplane is proposed. The multi-bit data storage can be achieved with a simple structure of two transistors and a capacitor, which controls the threshold voltage of a memory cell transistor exactly. In a memory cell, the low-temperature polycrystalline silicon (LTPS) TFT provides excellent stability against bias stress or current stress. In addition, the oxide semiconductor TFT enables the long-term data storage by virtue of its extremely low off-state leakage current. The proposed memory is fabricated with the LTPO TFT process which includes p-type LTPS and n-type oxide TFTs. Furthermore, the implementation of the multi-level property is successfully verified by measured results.

Влияние подслоя Ba-=SUB=-0.2-=/SUB=-Sr-=SUB=-0.8-=/SUB=-TiО-=SUB=-3-=/SUB=- на структуру и электрофизические характеристики пленок цирконата-титаната свинца на подложке Si(001)

Pb(ZrTi)O3/Ba0.2Sr0.8TiО3/Si(001) metal-ferroelectric-semiconductor hetero-structures were fabricated by radio-frequency cathodic sputtering. It was found that Pb(ZrTi)O3 films are single-phase, textured, and Ba0.2Sr0.8TiО3 sublayer thickness in-fluence on the texture preferred orientation (110 or 001). It has been shown that by varying the sublayer thickness and / or the amplitude of one period of the applied ex-ternal bipolar electric field, it is possible to create different electrophysical states of the structure. These electrophysical states can be used in creating of the memory cells and, in particular, a multi-level memory cells.

Area Efficient High Through-put Dual Heavy Metal Multi-Level Cell SOT-MRAM

This paper proposes a novel multi-level cell spin-orbit torque magnetic random-access memory (MLC SOT-MRAM) cell structure and validates its functionality and performance through simulation. The proposed memory cell comprises two uniform magnetic tunnel junctions (MTJs) that can be programmed separately by the energy efficient SOT technology through two different heavy metal electrodes. This permit employing both single and dual port architectures. The uniform cross-sectional area of the in-series MTJs stack simplifies the fabrication process. In addition, the cell structure requires only four terminals to successfully read and write the two bits. This allows accessing the two bits with only three access transistors, which achieves 25% smaller 1-bit effective area compared to the conventional single level cell (SLC) SOT-MRAM that requires four transistors. Simulation results based on an approximated dynamic model shows it offers nearly similar write energy consumption compared to the conventional SOT-MRAM.

Voltage Divider for Self-Limited Analog State Programing of Memristors

Resistive switching devices—memristors—present a tunable, incremental switching behavior. Tuning their state accurately, repeatedly and in a wide range, makes memristors well-suited for multi-level (ML) resistive memory cells and analog computing applications. In this brief, the tuning approach based on a memristor-resistor voltage divider (VD) is validated experimentally using commercial memristors from Knowm Inc . and a custom circuit. Rapid and controllable multi-state SET tuning is shown with an appreciable range of different resistance values obtained as a function of the amplitude of the applied voltage pulse. The efficiency of the VD is finally compared against an adaptive pulse-based tuning protocol, in terms of circuit overhead, tuning precision, tuning time, and energy consumption, qualifying as a simple hardware solution for fast, reliable, and energy-efficient ML resistance tuning.

Modeling of multilevel cell memory with theBaTiO3/Fenanostructured multiferroic composite material

In order to enhance the performance of calculators, multilevel cell (MLC) memories have been proposed as an alternative solution to improve the communication speed between their processors and memories, and also in order to increase the effective storage density of memory devices. In this Rapid Communication, we propose a model of MLC memory based on a multiferroic (MF) composite material. We introduce a one-dimensional trilayer ferromagnetic/ferroelectric/ferromagnetic MF composite material through which we investigate theoretically the dynamics of an electromagnon excitation displaying a soliton structure with an envelope shape. It emerges from this study based on barium titanate (${\text{BaTiO}}_{3}$) and iron (Fe) that, for suitable values of the parameters of a single initial polarization excitation, some propagation scenarios display the encoding of the states of a system of two magnetic bits, i.e., the 11, 10, 01, and 00 states. In addition to this result, it is also realized that the system exhibits another scenario for which the signal propagating in the MF material is alternately converted from an electrical signal into a magnetic signal and reversely. Such outcomes suggest, on the one hand, the possibility to model a four-level MLC memory, and on the other hand, the modeling of an electromagnetic oscillator, based on a MF composite material.

On the resistive switching mechanism of parylene-based memristive devices

Abstract Parylene is a widely used polymer possessing such advantages as low cost and safety for the human body. Recently, several studies have been conducted showing that parylene can be used as a dielectric layer of memristors — new circuit design elements that are promising for the implementation of hardware neural networks. However, the mechanism of resistive switching of parylene-based memristors remains unclear. In this paper, we report the result of a comprehensive study of this mechanism for Metal/Parylene/ITO sandwich memristive devices. The obtained results clearly show that the origin of resistive switching in the devices is the formation of conductive metal bridges (filaments) from the top electrode (Cu, Ag or Al) to the bottom one (ITO). And furthermore, conductance quantization effect with both integer and half-integer multiples of the quantum of conductance G0 = 2e2/h has been observed in the samples, which also confirms the chosen switching model, and can be useful in the development of multilevel data memory cells.

Multilevel information storage using magnetoelastic layer stacks

The use of voltages to control magnetisation via the inverse magnetostriction effect in piezoelectric/ferromagnet heterostructures holds promise for ultra-low energy information storage technologies. Epitaxial galfenol, an alloy of iron and gallium, has been shown to be a highly suitable material for such devices because it possesses biaxial anisotropy and large magnetostriction. Here we experimentally investigate the properties of galfenol/spacer/galfenol structures in which the compositions of the galfenol layers are varied in order to produce different strengths of the magnetic anisotropy and magnetostriction constants. Based upon these layers, we propose and simulate the operation of an information storage device that can operate as an energy efficient multilevel memory cell.

Demonstration of Multi-State Memory Device Combining Resistive and Magnetic Switching Behaviors

Resistively enhanced magnetic tunnel junction (Re-MTJ) nonvolatile memory devices with a heterogeneous structure of an MTJ surrounded by resistive filaments were investigated for the first time for multi-level cell memory applications. By independent control of the MTJ and the conductive filaments, multi-state resistances can be obtained since both resistive and magnetic switching can be accomplished in a single element. Compared with the conventional MTJs, the Re-MTJ devices have more resistance states without increasing the dimension. The advanced logic-in-memory applications can also be enabled by using conductive filaments and MTJs for logic and storage, respectively. A direct proof of concept was demonstrated by the experimental realization of memory encryption function using Re-MTJ devices with transparent feature.

Conductance Quantization in Nonvolatile Resistive Switching Memory Based on the Polymer Composite of Zinc Oxide Nanoparticles

The composite of zinc oxide (ZnO) and polyurethane (PU) was used as an active layer. The conductance quantization was demonstrated in nonvolatile resistive switching memory devices of the indium tin oxide/PU + ZnO/Al sandwich structure. The observed bipolar resistive switching behavior is estimated to arise from the formation and dissolution of Zn filaments. Furthermore, conductance quantization with both integer and half-integer multiples of G0 (2e2/h, where e is electron charge and h is Planck’s constant) has been observed in which multilevel conductance steps are separated by half-integer multiples of G0. The observed quantized conductance phenomena in multiple well-circumscribed resistance states were appropriate for application in multilevel data memory cells.

Neuron inspired data encoding memristive multi-level memory cell

Mapping neuro-inspired algorithms to sensor backplanes of on-chip hardware require shifting the signal processing from digital to the analog domain, demanding memory technologies beyond conventional CMOS binary storage units. Using memristors for building analog data storage is one of the promising approaches amongst emerging non-volatile memory technologies. Recently, a memristive multi-level memory cell for storing discrete analog values has been developed in which memory system is implemented combining memristors in voltage divider configuration. In given example, the memory cell of 3 sub-cells with a memristor in each was programmed to store ternary bits which overall achieved 10 and 27 discrete voltage levels. However, for further use of proposed memory cell in analog signal processing circuits data encoder is required to generate control voltages for programming memristors to store discrete analog values. In this paper, we present the design and performance analysis of data encoder that generates write pattern signals for 10 level memristive memory.