Multi-level Memory Cell Research Articles

A 1.8-V 128-Mb 125-MHz multilevel cell memory with flexible read while write

Application of multilevel cell (MLC) technology to a flexible read-while-write flash memory has been achieved through the use of a highly optimized sensing architecture. The goal of this implementation is to provide performance on par with single-bit-per-cell implementations while significantly reducing the overall die size. In order to achieve the required high-speed operation using MLC structures, all offsets to the sense amplifier were minimized and the column load and local sense amplifier were optimized to provide ample differential gain. Through the use of these optimization techniques, a 1.8-V MLC-based flexible read-while-write memory with 125-MHz continuous burst and 40-ns random read access time has been manufactured. Using a 0.13-μm technology, this new device provides a die size that is 25% of the size of the equivalent single-bit-per-cell device manufactured on a 0.18-μm technology.

Increasing storage capacity in multilevel memory cells by means of communications and signal processing techniques

Multilevel and analogue memory cells have the capability of storing considerably more than one bit of information per cell. The number of levels the memory cells can store is limited by noise and bit error probability. The authors propose using error correction coding and digital modulation techniques used in communication systems to increase the storage capacity of multilevel and analogue memory cells. They evaluate these techniques and find that compared to the methods that do not use coded modulation techniques, typically, one extra bit per cell (i.e. effectively doubling the number of levels per cell) in storage capacity can be achieved. The techniques can also be applied to improve readout bit-error probability and provide unequal error protection for the bits to be stored. The latter technique is important for the efficient storage of digitised multimedia signals such as speech, audio, image and video signals. One- and two-dimensional coded modulation schemes as well as uncoded multilevel digital modulation schemes are presented in detail. Complexity and speed issues are also considered.

Solid state [Technology 1998 analysis and forecast

Even as lithography further miniaturizes IC features, other advances are finessing device designs and the means of fabrication. Revisionist microprocessor architectures herald greater efficiency of instruction execution. Multilevel memory cells are doubling the storage density of flash chips. This year will see IC performance enhanced by the first implementations of copper interconnects. Beyond copper, engineers developing optical interconnections are waiting in the wings to show what their technology can do. Scientists find no dearth of potential lithographic tools for coming IC generations. To the contrary, industry leaders have several candidates to pick from: X-ray, projection electron-beam, extreme ultraviolet, and ion projection lithographies. But no technology has overcome all its obstacles and it is not at all clear which if any of the alternatives will emerge as the industry's tool of choice.

New operation mode for stacked-gate flash memory cell

A new operational mode is proposed that lowers the threshold voltage of a stacked-gate flash memory cell. The mode features the set-up of the word-line voltage and bit-line voltage. An AC signal is applied to a word-line while a bit-line is kept floating after it is charged. The signal is applied to lower the threshold voltage of the cell and to test it. A SPICE simulation of this operation has revealed that the converged voltage of floating gate has negligible dependency on the initial voltage and the tunnel oxide thickness and that the cell threshold voltage is controllable through the world-line voltage. This operation mode is easily applicable to a conventional flash memory. Furthermore, it may allow the use of flash cells in analog applications or in multi-level memory cells. >

Hall effect in adaptive threshold logic

Application of Hall effect to implement the adaptive threshold logic element is described. The adaptive weight unit described has a memory and a non-destructive read-out. The device consists of a Hall element inserted in an air-gap of a square-loop magnetic torroidal core. The generated Hall voltage represents the present effective weight. The memory is provided by the remanent flux in the core. The device described is essentially a multi-level memory cell with the direct electrical read-out.