Multi-level Cell Flash Memory Research Articles

DNN‐aided read‐voltage threshold optimization for MLC flash memory with finite block length

The error-correcting performance of multi-level-cell (MLC) NAND flash memory is closely related to the block length of error-correcting codes (ECCs) and log-likelihood-ratios of the read-voltage thresholds. Driven by this issue, this paper optimizes the read-voltage thresholds for MLC flash memory to improve the decoding performance of ECCs with finite block length. First, through the analysis of channel coding rate and decoding error probability under finite block length, the optimization problem of read-voltage thresholds to minimize the maximum decoding error probability is formulated. Second, a cross-iterative search algorithm to optimize read-voltage thresholds under the perfect knowledge of flash memory channel is developed. However, it is challenging to analytically characterize the voltage distribution under the effect of data retention noise. To address this problem, a deep neural network (DNN)-aided optimization strategy to optimize the read-voltage thresholds is developed, where a multi-layer perception network is employed to learn the relationship between voltage distribution and read-voltage thresholds. Simulation results show that, compared with the existing schemes, the proposed DNN-aided read-voltage threshold optimization strategy with a well-designed Low Density Parity Check (LDPC) code can not only improve the program-and-erase endurance but also reduce the read latency.

Syndrome-Coupled Rate-Compatible Error-Correcting Codes: Theory and Application

Rate-compatible error-correcting codes (ECCs), which consist of a set of extended codes, are of practical interest in both wireless communications and data storage. In this work, we first study the lower bounds for rate-compatible ECCs, thus proving the existence of good rate-compatible codes. Then, we propose a general framework for constructing rate-compatible ECCs based on cosets and syndromes of a set of nested linear codes. We evaluate our construction from two points of view. From a combinatorial perspective, we show that we can construct rate-compatible codes with increasing minimum distances, and we discuss decoding algorithms and correctable patterns of errors and erasures. From a probabilistic point of view, we prove that we are able to construct capacity-achieving rate-compatible codes, generalizing a recent construction of capacity-achieving rate-compatible polar codes. Applications of rate-compatible codes to data storage are considered. We design two-level rate-compatible codes based on Bose-Chaudhuri-Hocquenghem (BCH) and low-density parity-check (LDPC) codes which are two popular codes widely used in the data storage industry, and then we evaluate the performance of these codes in multi-level cell (MLC) flash memories. We also examine code performance on binary and $q$ -ary symmetric channels. Finally, we briefly discuss two variations of our main construction and their relative performance.

An Improved LDPC ECC based on System Level Reprogramming for MLC NAND Flash

With the ever-increasing requirement for higher performance of system and memory with a huge storage capacity, Multi-Level Cell (MLC) flash memory holds a dominant position in flash memory. However, more errors are observed in flash memory as the storage size increases. Thus, various error correction techniques (e.g., Hamming, BCH, LDPC) have been adopted to maintain the reliability of data stored in flash memory. Retention error, which occurs in data that is not accessed for a long period after stored, is the major contributor of flash memory error. The incidence of retention error is highly related to p-e (program-erase) cycle of flash memory. However, in system level, flash memory should be erased before modifying data even if ECC (Error correction code) decoding is completed. This erase operation increases the p-e cycle of flash memory, resulting in high incidence of retention error. This paper introduces a safe in-place reprogramming scheme at system level to optimally correct errors without erasing. Additionally, LDPC decoding scheme uses information about the uncorrected errors to improve the performance of the LDPC decoder. Through an experiment that simulates real NAND flash memory chips, safe reprogramming scheme at system level and proposed LDPC decoding method are explicitly demonstrated. As a result of proposed in-place reprogramming, reliable retention time of data is extended. Also, proposed LDPC decoding along with safe reprogramming scheme reduced the number of average iterations up to 33% while maintaining a robust correction ability.

Mitigation of 2D-ICI in Flash Memory Using Hierarchical Constrained Codes

Inter-cell interference (ICI) significantly affects the reliability of flash memory. Both horizontal and vertical ICI have been taken into account for the errors in flash memory. In this paper, we propose a two-dimensional hierarchical constrained code (2D-HCC) to mitigate both horizontal and vertical ICIs of flash memory. The proposed scheme is applied to both single-level cell (SLC) and multi-level cell (MLC) flash memory. Finally, the bit error rate (BER) of the proposed 2D-HCC with/without Bose-Chaudhuri-Hocquenghem (BCH) codes is simulated. The simulated results confirm the advantage of the proposed scheme.

Interpage-Based Endurance-Enhancing Lower State Encoding for MLC and TLC Flash Memory Storages

During the past decade, the endurance of NAND flash memory has severely deteriorated. The maximum number of program and erase cycles has fallen significantly with emerging of multilevel cell (MLC) and triple-level cell (TLC) technology, and scaling down of the cell size. Wear leveling is a general solution used to alleviate this issue; it enables cells to wear down evenly but it cannot actually mitigate the wearing of the cells. Accordingly, techniques are required to minimize the actual cell degradation. This paper proposes <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">endurance-enhancing lower state encoding</i> . The key insight leveraged by the proposed technique is the data pattern-related characteristic of MLC and TLC NAND flash memories, in which the lower the state of the cells, the lower the occurrence of wear out. Thus, our proposed scheme encodes input data to make the cell state as low as possible in consideration of interpage relation. As a result, the wear out of the memory cells can be minimized and their lifetime is improved by 62.7% in a file type and 43.0% in MySQL. Experimental results indicate that our scheme shows better lifetime improvement than other schemes in most cases.

On the distribution of the threshold voltage in multi-level cell flash memories

In Multi-Level Cell (MLC) memories, multiple bits of information are packed within the cell to enable higher capacity and lower cost of manufacturing compared to those of the single-level cell flash. However, because of heavy information packing, MLC memories suffer from several error sources including inter-cell interference, retention error, and random telegraph noise which make their lifetime shorter. Having so many error sources that are statistically hard to characterize makes it challenging to properly derive the underlying probability distribution of the sensed threshold voltage, which is vital for finding optimal decision rules to secure better detection performance and hence better lifetime. Although several recent works have already considered this problem, they mostly recourse to few loose assumptions that are far from being realistic. In this study, a more comprehensive/general analysis is conducted to derive the probability density function of the final sensed voltage, and through realistic simplifications, closed form expressions are presented. Extensive computer simulations corroborate the accuracy of the derived analytical expressions, and we think they shall be essential for accurately estimating the reliability and the overall lifetime of modern MLC memories.

Capacity-Achieving Codes That Mitigate Intercell Interference and Charge Leakage in Flash Memories

We investigate constant-composition constrained codes for the mitigation of intercell interference for multilevel cell flash memories with a dynamic threshold scheme. The first explicit formula for the maximum size of a $q$ -ary ${\mathcal F}$ -avoiding code with a given composition and certain families of substrings ${\mathcal F}$ is presented. In addition, we provide methods to determine the asymptotic rate for ${\mathcal F}$ -avoiding codes with any composition ratio and to find the optimal composition ratio that maximizes the asymptotic rate. We also give the first efficient encoder/decoder for these $q$ -ary constant-composition codes achieving the channel capacity, for all $q$ values.

Protograph QC-LDPC and Rate-Adaptive Polar Codes Design for MLC NAND Flash Memories

A protograph-based quasi-cyclic (QC) low-density parity-check (LDPC) code for multi-level cell (MLC) NAND flash memories is proposed in this paper. In this design approach, the quantized voltage signals are measured for soft decoding because the exact voltage values are unavailable. Flash memory channels are asymmetric, and therefore, not optimal for existing LDPC codes optimized for symmetric additive white Gaussian noise (AWGN)-like channels. Mutual information (MI) between the input and output of flash memory is used to model the quantized log-likelihood ratio (LLR) messages. The base matrix of the method is constructed according to the degree sequences optimized by the modified extrinsic information transfer (EXIT) chart method for flash memories. The designed protograph-based codes have a low-complexity QC encoder structure with a readily parallelizable decoder structure. In addition, rate-adaptive polar code design based on Bhattacharyya parameters of the memory cell bits is proposed to further improve the storage efficiency of the MLC NAND flash memories. The code design takes advantage of the inherent characteristics of MLC flash memory channel to iteratively calculate the Bhattacharyya parameter of each memory cell bit, where the punctured positions are selected by choosing the bits with higher Bhattacharyya parameters to construct rate-adaptive polar codes. The simulation results confirm the benefits of the proposed coding schemes.

An SLC-Like Programming Scheme for MLC Flash Memory

Although the multilevel cell (MLC) technique is widely adopted by flash-memory vendors to boost the chip density and lower the cost, it results in serious performance and reliability problems. Different from past work, a new cell programming method is proposed to not only significantly improve chip performance but also reduce the potential bit error rate. In particular, a single-level cell (SLC)-like programming scheme is proposed to better explore the threshold-voltage relationship to denote different MLC bit information, which in turn drastically provides a larger window of threshold voltage similar to that found in SLC chips. It could result in less programming iterations and simultaneously a much less reliability problem in programming flash-memory cells. In the experiments, the new programming scheme could accelerate the programming speed up to 742% and even reduce the bit error rate up to 471% for MLC pages.

LLR-Distribution-Based Non-Uniform Quantization for RBI-MSD Algorithm in MLC Flash Memory

Multi-level cell (MLC) technique has been widely used to improve the storage capacity of NAND flash memory at the price of sacrificing some storage reliability. As a type of excellent error-correction codes, low-density parity-check (LDPC) codes can significantly enhance the performance of flash memory. However, the conventional decoding algorithms for LDPC codes suffer from the drawback of high complexity. To address this problem, we propose a serial reliability-based iterative min-sum decoding (RBI-MSD) algorithm for LDPC-coded MLC flash memory systems to strike a desirable trade-off between the performance and complexity. Furthermore, we conceive a novel log-likelihood-ratio (LLR)-distribution-based non-uniform quantization method for the RBI-MSD algorithm. Unlike conventional quantization methods, the proposed non-uniform quantization method substantially exploits the distribution characteristics of channel initial LLRs in MLC flash memory. Simulation results indicate that the proposed non-uniform quantization method not only exhibits more excellent error performance than the conventional non-uniform and uniform counterparts, but also is applicable to other RBI decoding algorithms.

Row-by-Row Coding Schemes for Inter-Cell Interference in Flash Memory

Inter-cell interference (ICI) is a significant cause of errors in flash memories. In single-level cell (SLC) flash memory, ICI arises when 1 0 1 patterns are programmed either in the horizontal or vertical directions. Since data pages are written sequentially in horizontal wordlines, one can mitigate the effects of horizontal ICI by applying conventional constrained codes that forbid the 1 0 1 pattern. This approach does not address the problem of vertical ICI, however. In this paper, a row-by-row coding technique that eliminates vertical 1 0 1 patterns while preserving the sequential wordline programming order is presented. This scheme, though efficient, necessarily suffers a rate loss of almost 20%. We therefore propose another coding scheme, combining a weak constraint on vertical 1 0 1 patterns with a systematic error-correcting code, that can mitigate vertical ICI errors while achieving a higher overall coding rate, provided that the vertical ICI error probability is sufficiently small. Some extensions for multi-level cell (MLC) flash memory are discussed as well.

On the Capacity of the Beta-Binomial Channel Model for Multi-Level Cell Flash Memories

The beta-binomial (BBM) channel model was recently proposed to model the overdispersed statistics of empirically observed bit errors in multi-level cell (MLC) flash memories. In this paper, we study the capacity of the BBM channel model for MLC flash memories. Using the compound channel approach, we first show that the BBM channel model capacity is zero. However, through empirical observation, this appears to be a very pessimistic estimate of the flash memory channel capacity. We propose a refined channel model called the truncated-support beta-binomial (TS-BBM) channel model and derive its capacity. Using empirical error statistics from 1X-nm and 2Y-nm MLC flash memories, we numerically estimate the TS-BBM channel model capacity as a function of the program/erase (P/E) cycling stress. The capacity of the 2-TS-BBM channel model provides an upper bound on the coding rates for the flash memory chip assuming a single binary error correction code is used.

Performance of Multilevel Flash Memories With Different Binary Labelings: A Multi-User Perspective

In this paper, we study the performance of different decoding schemes for multilevel flash memories where each page in every block is encoded independently. We focus on multi-level cell flash memory, which is modeled as a two-user multiple-access channel suffering from asymmetric noise. The uniform rate regions and sum rates of treating interference as noise decoding and successive cancelation decoding are investigated for a program/erase cycling model and a data retention model. We examine the effect of different binary labelings of the cell levels, as well as the impact of further quantization of the memory output (i.e., additional read thresholds). Finally, we extend our analysis to the three-level cell flash memory.

Modeling of Threshold Voltage Distribution in NAND Flash Memory: A Monte Carlo Method

NAND flash reliability (both endurance and retention) degrades with the scaling of NAND flash memory technology and the introduction of multilevel cell (MLC) and triple-level cell (TLC) technologies. As a result, stronger error correction code (ECC) methods are required in the solid-state drive application, especially for MLC and TLC flash memory devices. Modeling of the threshold voltage ( $V_{t}$ ) distribution in the NAND flash memory can make the ECC simulations more effective and efficient. In this paper, we show a semiphysical and Monte Carlo method to generate a reallike $V_{t}$ distribution by mimicking the NAND flash programming and data retention (DR) processes. Probability distributions used in the Monte Carlo method are obtained by the measurements of the NAND devices and data interpolation or extrapolation. Simulations by this model can obtain reallike $V_{t}$ distribution for any given Program/Erase cycle and DR time. Excellent results have been obtained and confirmed by comparing the simulations with the measured data from 16-nm NAND flash devices.

Polar Code Design for Noisy Blackwell Channels

In this letter, we introduce a class of discrete memoryless broadcast channels, called noisy Blackwell channels, which generalize the Blackwell channel to include noise and to more than two users. We design the polar code for the noisy Blackwell channel based on Marton’s coding scheme. We choose auxiliary random variables and the mapping from auxiliary random variables to the channel input, such that the sum-rate capacity can be achieved very closely. Furthermore, we show that the designed polar code can be applied to multi-level cell flash memories for improving random I/O performance. The simulation results demonstrate that our designed polar codes achieve good performance even for a large number of users.

Channel Models for Multi-Level Cell Flash Memories Based on Empirical Error Analysis

We propose binary discrete parametric channel models for multi-level cell (MLC) flash memories that provide accurate ECC performance estimation by modeling the empirically observed error characteristics under program/erase (P/E) cycling stress. Through a detailed empirical error characterization of 1X-nm and 2Y-nm MLC flash memory chips from two different vendors, we observe and characterize the overdispersion phenomenon in the number of bit errors per ECC frame. A well studied channel model such as the binary asymmetric channel (BAC) model is unable to provide accurate ECC performance estimation. Hence we propose a channel model based on the beta-binomial probability distribution (2-BBM channel model) which is a good fit for the overdispersed empirical error characteristics and show through statistical tests and simulation results for BCH, LDPC and polar codes, that the 2-BBM channel model provides accurate ECC performance estimation in MLC flash memories.

Adaptive ECC Scheme for Hybrid SSD’s

In recent years, multi-level cell flash memory (MLC) has been widely adopted in solid state drives (SSD’s) as the major storage medium due to its lower cost and higher density, compared with single-level cell flash memory (SLC). However, MLC has reliability concerns since it has lower endurance and higher disturb failure rate. Researchers thus proposed SLC/MLC hybrid SSD to exploit the advantages of SLC and MLC by separating frequently updated data in SLC and seldom modified data in MLC. In this paper, we propose an adaptive error correction code (ECC) scheme with four ECC levels to enhance the reliability of SSD’s. Different from past researches, SLC is dedicated for the management of ECC, not for the user data. Since ECC is maintained in the data area of SLC (2 KB), rather than the spare area of MLC (128 Bytes), ECC capability is no longer confined by the limited size of the spare area. With adaptive management, ECC capability for a page would be upgraded whenever the current ECC cannot guarantee its reliability. A quantitative analysis is conducted to explore the impacts of different settings. The experiment results show that the lifetime of SSD can be extended by 318 percent for the trace of OLTP applications with our adaptive ECC scheme.

Modelling and characterization of NAND flash memory channels

The threshold voltage distribution after ideal programming in NAND flash memory cells is usually distorted by a combination of the random telegraph noise (RTN), cell-to-cell interference (CCI), and the retention process. To decide the original bits more accurately in this scenario, a precise channel model shall be utilized on the basis of the measured threshold voltages. This paper aims to characterize these various distortions occurring in multi-level cell (MLC) flash memories. A mathematical description of the overall distribution for the total flash channel distortion is presented. The final threshold voltage distribution for each symbol of MLC flash is also characterized, which is important for calculating the exact soft decisions of cell bits and the application of advanced flash error correction. The results of the theoretical analysis have been validated through Monte Carlo simulations of the flash channel.

Improving Performance and Capacity of Flash Storage Devices by Exploiting Heterogeneity of MLC Flash Memory

The multi-level cell (MLC) NAND flash memory technology enables multiple bits of information to be stored in a memory cell, thus making it possible to increase the density of flash memory without increasing the die size. In MLC NAND flash memory, each memory cell can be programmed as a single-level cell or a multi-level cell at runtime because of its performance/capacity asymmetric programming property, which is called flexible programming in this paper. Therefore, MLC flash memory has a potential to achieve the high performance of SLC flash memory while preserving its maximum capacity. In this paper, we present a flexible flash file system, called FlexFS, which takes advantage of flexible programming. FlexFS divides a flash memory medium into SLC and MLC regions, and then dynamically changes two different types of regions to provide an optimal storage solution to end-users in terms of performance and capacity. FlexFS also provides a reasonable storage lifetime by managing the wearing rate of NAND flash memory, which is accelerated by the use of flexible programming. Our implementation of FlexFS in the Linux 2.6 kernel shows that it achieves the I/O performance comparable to SLC flash memory while guaranteeing the capacity of MLC flash memory in various real-world workloads.

Adaptive Paired Page Prebackup Scheme for MLC NAND Flash Memory

Multilevel cell (MLC) NAND flash memory is more cost effective compared with single-level cell NAND flash memory as it can store two or more bits in a memory cell. However, in MLC flash memory, a programming operation can corrupt the paired page under abnormal termination. In order to solve the paired page problem, a backup scheme is generally used, which inevitably causes performance degradation and shortens the lifespan of flash memory. In this paper, we propose a more efficient paired page prebackup scheme for MLC flash memory. It adaptively exploits interleaving, copyback operations, and parity data to reduce the prebackup overhead. In experiments, the proposed scheme reduced the backup overhead by up to 78%.