Abstract
The error-correcting performance of multi-level-cell (MLC) NAND flash memory is closely related to the block length of error-correcting codes (ECCs) and log-likelihood-ratios of the read-voltage thresholds. Driven by this issue, this paper optimizes the read-voltage thresholds for MLC flash memory to improve the decoding performance of ECCs with finite block length. First, through the analysis of channel coding rate and decoding error probability under finite block length, the optimization problem of read-voltage thresholds to minimize the maximum decoding error probability is formulated. Second, a cross-iterative search algorithm to optimize read-voltage thresholds under the perfect knowledge of flash memory channel is developed. However, it is challenging to analytically characterize the voltage distribution under the effect of data retention noise. To address this problem, a deep neural network (DNN)-aided optimization strategy to optimize the read-voltage thresholds is developed, where a multi-layer perception network is employed to learn the relationship between voltage distribution and read-voltage thresholds. Simulation results show that, compared with the existing schemes, the proposed DNN-aided read-voltage threshold optimization strategy with a well-designed Low Density Parity Check (LDPC) code can not only improve the program-and-erase endurance but also reduce the read latency.
Highlights
N AND flash memory is widely used over the past decade due to low power consumption and large storage capacity
As the number of levels in each memory cell increases, serious scaling challenges loom up in the NAND flash memory, resulting in a negative effect on the reliability. These challenges originate from the characteristics of flash devices that can be seen as several noise models, such as programming noise (PN), cell-to-cell interference (CCI), random telegraph noise (RTN), and data retention noise (DRN) [4]
Based on the finite block length theory, we converted the problem of maximizing channel coding rate (CCR) problem into that of minimizing the maximum decoding error probability
Summary
N AND flash memory is widely used over the past decade due to low power consumption and large storage capacity. As the number of levels in each memory cell increases, serious scaling challenges loom up in the NAND flash memory, resulting in a negative effect on the reliability. These challenges originate from the characteristics of flash devices that can be seen as several noise models, such as programming noise (PN), cell-to-cell interference (CCI), random telegraph noise (RTN), and data retention noise (DRN) [4]. As the size of memory chip decreases, the floating-gate of a flash memory cell stores much fewer electrons, which degrades the performance of flash memory This is due to the fact that a small amount of charge leakage has remarkable influence on the floatinggate transistor. The increasing number of program-and-erase (PE) cycles and the DRT limit the operational lifetime of flash memory
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