Multi-core Platforms Research Articles

Double-Layer Energy Efficient Synchronous-Asynchronous Circuit-Switched NoC

A network-on-chip (NoC) offers high performance, flexibility and scalability in communication infrastructure within multi-core platforms. However, NoCs contribute significantly to the overall system’s power consumption. The double-layer energy efficient synchronous-asynchronous circuit-switched NoC (CS-NoC) is proposed to enhance the power utilization. To reduce the dynamic power consumption, single-rail asynchronous protocols are utilized. The two-phase and four-phase encoding algorithms are analyzed to determine the most efficient technique. For the data layer, the two asynchronous protocols reduced the power consumption by 80%, with an increase in latency when compared with the fully synchronous protocol. However, the two-phase single-rail protocol had better performance compared with the four-phase protocol by 38%, with the same power consumption and a slight increase in area of 5%. Based on this conducted analysis, the asynchronous two-phase layer had significant power reduction yet operated at a moderate frequency. Therefore, the proposed NoC is divided into two data transfer layers with a single control layer. The data transfer layers are designed using synchronous and asynchronous protocols. The synchronous layer is designated to high-frequency loads, and the asynchronous layer is confined to low-frequency loads. The switching between the layers creates a trade-off between the maximum allowed frequency and the power consumption. The proposed NoC reduces the overall power consumption by 23% when compared with recent previous work. The NoC maintains the same system performance with an 8% area increase over the fully synchronous double-layer in the literature.

DE-striping Augmented Images of Blood Cells using Deep Convolutional Neural Network

The aim of this biomedical image processing-based research paper is to use augmented images of blood sample and Deep Convolutional Neural Network (DCNN) for the purpose of de-striping on Hyperion data to de-stripe on multicore platforms GPU. In order to reach our goal, we have started by analyzing the challenges associated with de-striping, Hyperion data and DCNN. A novel implementation pipeline of training, validating and evaluating stating from input an augmented blood image sample with the help analyzing the Hyperion data leading to the de-striping of augmented image blood sample by removing all the kernel black. What is clear is the high importance of applying the adequate pre-processing on Hyperion data because of low signal-to-noise ratio. By comparing the known layers of DCNN model for de-striping augmented images. The results obtained by applying the mentioned methods, it is revealed that all the higher stripes in an image as well as black color has been reduced and entirely associated with the Hyperion data alteration, and in contrast, the Hyperion imagery successfully corresponds to the de-striping of augmented image with an accuracy of 91.89% using DCNN model. The proposed DCNN is capable of reaching high accuracy within 150s after the launch of the evaluation phase and never reaches low accuracy. The pre-trained DCNN model approach would be an adequate solution considering de-striping as its high inference time is lower compared existing available methods which are not as efficient for de-striping.

Efficient parallelization of SPH algorithm on modern multi-core CPUs and massively parallel GPUs

Smoothed Particle Hydrodynamics (SPH) is fast emerging as a practically useful computational simulation tool for a wide variety of engineering problems. SPH is also gaining popularity as the back bone for fast and realistic animations in graphics and video games. The Lagrangian and mesh-free nature of the method facilitates fast and accurate simulation of material deformation, interface capture, etc. Typically, particle-based methods would necessitate particle search and locate algorithms to be implemented efficiently, as continuous creation of neighbor particle lists is a computationally expensive step. Hence, it is advantageous to implement SPH, on modern multi-core platforms with the help of High-Performance Computing (HPC) tools. In this work, the computational performance of an SPH algorithm is assessed on multi-core Central Processing Unit (CPU) as well as massively parallel General Purpose Graphical Processing Units (GP-GPU). Parallelizing SPH faces several challenges such as, scalability of the neighbor search process, force calculations, minimizing thread divergence, achieving coalesced memory access patterns, balancing workload, ensuring optimum use of computational resources, etc. While addressing some of these challenges, detailed analysis of performance metrics such as speedup, global load efficiency, global store efficiency, warp execution efficiency, occupancy, etc. is evaluated. The OpenMP and Compute Unified Device Architecture[Formula: see text] parallel programming models have been used for parallel computing on Intel Xeon[Formula: see text] E5-[Formula: see text] multi-core CPU and NVIDIA Quadro M[Formula: see text] and NVIDIA Tesla p[Formula: see text] massively parallel GPU architectures. Standard benchmark problems from the Computational Fluid Dynamics (CFD) literature are chosen for the validation. The key concern of how to identify a suitable architecture for mesh-less methods which essentially require heavy workload of neighbor search and evaluation of local force fields from neighbor interactions is addressed.

Improving the speed of global parallel optimization on PDE models with processor affinity scheduling

AbstractParallel global optimization of expensive simulation models like nonlinear partial differential equations (PDEs) can speed up model calibration or project design decisions, but the impact of memory management on the efficiency of using parallel global optimization methods has not been previously studied. This paper quantifies cache memory limitations arising during parallel optimization of expensive PDE models. An efficient parallel optimization algorithm is applied to model calibration for two different, expensive real‐world PDEs (i.e., hydrodynamic and water quality analysis for a 250‐hectare lake). One of these two lake models takes 4.5 h per simulation in serial, but that PDE simulation time per simulation increases to 12 h with parallel optimization if default processor scheduling strategy is used on a modern nonuniform memory access multicore platform. We proposed a novel mixed affinity scheduling strategy for parallel simulation optimization that increases computational efficiency by as much as 20% over the default affinity strategy.

Mitigating the processor aging through dynamic concurrency throttling

The increase in the number of cores in a single chip brings better capabilities to exploit thread-level parallelism (TLP). However, since power dissipated per area rises at each new node generation, higher temperatures are achieved, speeding up the aging of hardware components, which may provoke undesired system behavior. Considering that many applications do not scale with the number of cores, their execution with the maximum TLP available will not only degrade performance, but also unnecessarily increase temperature, further accelerating aging. Given that, we propose Hebe, a dynamic concurrency throttling approach that learns at run-time the degree of TLP that reduces the aging for OpenMP applications. Hebe is totally transparent, needing no modifications in the original binary code. With a set of extensive experiments (fifteen benchmarks and four multicore platforms), we show that Hebe outperforms state-of-the-art approaches with very close results from the best possible solution given by an exhaustive search.

ARINC653 Channel Robustness Verification Using LeonViP-MC, a LEON4 Multicore Virtual Platform

Multicore hardware platforms are being incorporated into spacecraft on-board systems to achieve faster and more efficient data processing. However, such systems lead to increased complexity in software development and represent a considerable challenge, especially concerning the runtime verification of fault-tolerance requirements. To address the ever-challenging verification of this kind of requirement, we introduce a LEON4 multicore virtual platform called LeonViP-MC. LeonViP-MC is an evolution of a previous development called Leon2ViP, carried out by the Space Research Group of the University of Alcalá (SRG-UAH), which has been successfully used in the development and testing of the flight software of the instrument control unit (ICU) of the energetic particle detector (EPD) on board the Solar Orbiter. This paper describes the LeonViP-MC architectural design decisions oriented towards fault-injection campaigns to verify software fault-tolerance mechanisms. To validate the simulator, we developed an ARINC653 communications channel that incorporates fault-tolerance mechanisms and is currently being used to develop a hypervisor level for the GR740 platform.

Workload assignment for global real-time scheduling on unrelated clustered platforms

Heterogeneous MPSoCs are being used more and more, from cellphones to critical embedded systems. Most of those systems offer heterogeneous sets of identical cores. In this paper, we propose new results on the global scheduling approach. We extend fundamental global scheduling results on unrelated processors to results on unrelated multicore platforms, a more realistic model. We introduce several methods to construct the workload assignment of tasks to cores taking advantage of this new model. Every studied result is optimal regarding schedulability, and all the proposed methods but one have a polynomial time complexity. Thanks to the model, the produced schedules have a limited degree of migrations. The benefits of the methods are demonstrated and compared using synthetic tasks sets. Practical limitations of the global scheduling approach on unrelated platforms are discussed, but we argue that it is still worth investigating considering modern MPSoCs.

Memory-Aware Scheduling Parallel Real-Time Tasks for Multicore Systems

Shared resources on the multicore chip, such as main memory, are increasingly becoming a point of contention. Traditional real-time task scheduling policies focus on solely on the CPU, and do not take in account memory access and cache effects. In this paper, we propose parallel real-time tasks scheduling (PRTTS) policy on multicore platforms. Each set of tasks is represented as a directed acyclic graph (DAG). The priorities of tasks are assigned according to task periods Rate Monotonic (RM). Each task is composed of three phases. The first phase is read memory stage, the second phase is execution phase and the third phase is write memory phase. The tasks use locks and critical sections to protect data access. The global scheduler maintains the task pool in which tasks are ready to be executed which can run on any core. PRTTS scheduling policy consists of two levels: the first level scheduling schedules ready real-time tasks in the task pool to cores, and the second level scheduling schedules real-time tasks on cores. Tasks can preempt the core on running tasks of low priority. The priorities of tasks which want to access memory are dynamically increased above all tasks that do not access memory. When the data accessed by a task is in the cache, the priority of the task is raised to the highest priority, and the task is scheduled immediately to preempt the core on running the task not accessing memory. After accessing memory, the priority of these tasks is restored to the original priority and these tasks are pended, the preempted task continues to run on the core. This paper analyzes the schedulability of PRTTS scheduling policy. We derive an upper-bound on the worst-case response-time for parallel real-time tasks. A series of extensive simulation experiments have been performed to evaluate the performance of proposed PRTTS scheduling policy. The results of simulation experiment show that PRTTS scheduling policy offers better performance in terms of core utilization and schedulability rate of tasks.

Flexible On-Line Reconfiguration of Multi-Core Neuromorphic Platforms

Neuromorphic architectures are emerging not only for real-time simulation of brain-scale biological neural networks but also to support innovative brain-inspired computational paradigms. In both domains there is an increasing demand for flexibility in terms of network configuration and runtime redesign of network parameters and simulated neurons models. Due to the intrinsically high parallelism of these architectures and complexity of the interconnect, broadcasting updates to the cores is time consuming. Hence, static solutions where the network is reloaded from an external host instead of being reconfigured are highly inefficient. To address these requirements, we designed an Application Command Protocol (ACP). The proposed protocol provides a mechanism to remotely trigger the execution of high-level op-codes by the cores and manage their application memory, and supports a more flexible computational model and memory management. We worked on SpiNNaker, a multi-core globally-asynchronous locally-synchronous platform running Spiking Neural Networks (SNNs) simulations. We demonstrated ACP in two SNN applications: i) SNN configuration, where simulation data are efficiently generated through ACP in the memory of computing nodes and ii) SNN reconfiguration, where ACP is used to change SNN network parameters at runtime and to easily switch from learning to test phase in a SNN classification application.

A systematic methodology to migrate complex real-time software systems to multi-core platforms

This paper proposes a systematic three-stage methodology for migrating complex real-time industrial software systems from single-core to multi-core computing platforms. Single-core platforms have limited computational capabilities that prevent integration of computationally demanding applications such as image processing within the existing system. Modern multi-core processors offer a promising solution to address these limitations by providing increased computational power and allowing parallel execution of different applications within the system. However, the transition from traditional single-core to contemporary multi-core computing platforms is non-trivial and requires a systematic and well-defined migration process. This paper reviews some of the existing migration methods and provides a systematic multi-phase migration process with emphasis on software architecture recovery and transformation to explicitly address the timing and dependability attributes expected of industrial software systems. The methodology was evaluated using a survey-based approach and the results indicate that the presented methodology is feasible, useable and useful for real-time industrial software systems.

A systematic methodology to migrate complex real-time software systems to multi-core platforms

A systematic methodology to migrate complex real-time software systems to multi-core platforms

Design, analysis and performance evaluation of parallel algorithms for solving triangular linear systems on multicore platforms

In this paper, we focus on the schedulings of 2-steps graph with constant task cost obtained when parallelizing algorithm solving a triangular linear system. We present three scheduling approaches having the same least theoretical execution time. The first is designed through solving a 0-1 integer problem by Mixed Integer Programming (MIP), the second is based on the Critical Path Algorithm (CPA) and the third is a particular Column-Oriented Scheduling (COS). The MIP approach experiments were carried out and confirmed that the makespan values of the MIP scheduling coincide with those of the corresponding lower bound already reached. Experimental results of the last two approaches detailing both makespans and efficiencies are presented and show that their practical performances differ though they are theoretically identical. We compare also these results to those of the appropriate procedure into so-called PLASMA library (Parallel Linear Algebra for Scalable Multi-core Architectures).

Randomized Constraints Consensus for Distributed Robust Mixed-Integer Programming

In this article, we consider a network of processors aiming at cooperatively solving mixed-integer convex programs subject to uncertainty. Each node only knows a common cost function and its local uncertain constraint set. We propose a randomized, distributed algorithm working under asynchronous, unreliable, and directed communication. The algorithm is based on a local computation and communication paradigm. At each communication round, nodes perform two updates: 1) A verification in which they check—in a randomized fashion—the robust feasibility of a candidate optimal point, and 2) an optimization step in which they exchange their candidate basis (the minimal set of constraints defining a solution) with neighbors and locally solve an optimization problem. As a main result, we show that processors can stop the algorithm after a finite number of communication rounds (either because verification has been successful for a sufficient number of rounds or because a given threshold has been reached) so that candidate optimal solutions are consensual. The common solution has proven to be—with high confidence—feasible and, hence, optimal for the entire set of uncertainty except a subset having an arbitrarily small probability measure. We show the effectiveness of the proposed distributed algorithm using two examples: a random, uncertain mixed-integer linear program and a distributed localization in wireless sensor networks. The distributed algorithm is implemented on a multicore platform in which the nodes communicate asynchronously.

Concurrent Application Bias Scheduling for Energy Efficiency of Heterogeneous Multi-Core Platforms

Minimizing energy consumption of concurrent applications on heterogeneous multi-core platforms is challenging given the diversity in energy-performance profiles of both the applications and hardware. Adaptive learning techniques made the exhaustive Pareto-optimal space exploration practically feasible to identify an energy efficient configuration. Existing approaches consider a single application's characteristic for optimizing energy consumption. However, an optimal configuration for a given application in isolation may not be optimal when other applications are run concurrently. Approaches that consider concurrent application scenarios overlook the weight of total energy consumption per application, restricting them from prioritizing among applications. We address this limitation by considering the mutual effect of concurrent applications on system wide energy consumption to adapt resource configuration at run-time. We characterize each application's power-performance profile as a weighted bias through off-line profiling. We infer this model combined with an on-line predictive strategy to make resource allocation decisions for minimizing energy consumption while honoring performance requirements. The proposed strategy is implemented as a user-space process and evaluated on a heterogeneous hardware platform of Odroid XU3 over the Rodinia benchmark suite. Experimental results show up to 61 percent of energy saving compared to the standard baseline of Linux governors and up to 27 percent of energy gain compared to state-of-the-art adaptive learning-based resource management techniques.

Improving the accuracy of energy predictive models for multicore CPUs by combining utilization and performance events model variables

Energy predictive modeling is the leading method for determining the energy consumption of an application. Performance monitoring counters (PMCs) and resource utilizations have been the principal source of model variables primarily due to their high positive correlation with energy consumption. Performance events, however, have come to dominate the landscape due to their better prediction accuracy compared to utilization variables. Recently, the theory of energy of computing has been proposed whose practical implications for constructing accurate and reliable linear energy predictive models are unified in a consistency test that includes a selection criterion of additivity for model variables. In this work, we analyze the prediction accuracy of models employing utilization variables only, PMCs only, and combination of both utilization variables and PMCs, through the lens of this theory for modern multicore CPU platforms. We discover that employing utilization variables only in linear energy predictive models does not capture all the energy-consuming activities during an application execution. However, combination of utilization variables with PMCs that are highly additive and highly correlated with energy consumption, gives the most accurate linear energy predictive model. Our experimental results show that application-specific and platform-level models using both utilization variables and PMCs exhibit up to 3.6× and 2.6× better average prediction accuracy respectively when compared with models employing utilization variables only and highly additive PMCs only.

Toward Practical Weakly Hard Real-Time Systems: A Job-Class-Level Scheduling Approach

Recent applications of the Internet of Things and cyber–physical systems require the integration of many sensing and control tasks into resource-constrained embedded devices. Such tasks can often tolerate a bounded number of timing violations. The concept of weakly hard real-time systems can effectively improve resource efficiency without sacrificing system safety. However, the existing studies have limitations on their practical use due to the restrictions imposed on the task timing behavior, high analysis complexity, and the lack of multicore support. In this article, we propose a new job-class-level fixed-priority preemptive scheduler and its schedulability analysis framework for weakly hard real-time tasks. Our proposed scheduler employs the meet-oriented classification of jobs of a task in order to reduce the worst-case temporal interference imposed on other tasks. Under this approach, each job is associated with a “job-class” that is determined by the number of deadlines previously met (with a bounded number of consecutively missed deadlines). This approach allows decomposing the complex weakly hard schedulability problem into two subproblems that are easier to solve: 1) analyzing the response time of a job with each job-class, which can be done by an extension of the existing task-level analysis and 2) finding possible job-class patterns, which can be modeled as a simple reachability tree. We also present a semipartitioned task allocation method for multicore platforms, which enhances the schedulability of weakly hard tasks under the proposed scheduling framework. Experimental results indicate that our scheduler outperforms the prior work in terms of task schedulability and analysis time complexity. We have also implemented a prototype of a job-class-level scheduler in the Linux kernel running on Raspberry Pi with acceptably small-runtime overhead.

Dynamic task allocation and scheduling with contention-awareness for Network-on-Chip based multicore systems

Abstract In recent years, Network-on-Chip (NoC) based multicore systems have become popular for executing real-time applications. Mapping and scheduling of these applications are critical for system performance. The complexity of the problem increases for dynamic scenarios with real-time applications where new applications unknown at design-time, are submitted by users at runtime. Most of the existing works in this domain either ignore the allocation of communication workload or use estimated network contention while neglecting the impact on timing performance of tasks. In this work, we present an improved algorithm for dynamic task assignment and scheduling with link contention-awareness, which jointly allocates the tasks on the processors of NoC based multicore platform and schedules the communications on on-chip links. It minimizes communication latency and helps to satisfy the deadline of the tasks present in the allocated real-time applications. Experimental results show that the proposed approach achieves 25.3% and 45.6% improvement in task deadline satisfaction and communication latency compared to recent dynamic task allocation approaches while exhibiting 31.2% reduced runtime overhead.

Software synthesis from dataflow schedule graphs

The dataflow-model of computation is widely used in design and implementation of signal processing systems. In dataflow-based design processes, scheduling—the assignment and coordination of computational modules across processing resources—is a critical task that affects practical measures of performance, including latency, throughput, energy consumption, and memory requirements. Dataflow schedule graphs (DSGs) provide a formal abstraction for representing schedules in dataflow-based design processes. The DSG abstraction allows designers to model a schedule as a separate dataflow graph, thereby providing a formal, abstract (platform- and language-independent) representation for the schedule. In this paper, we introduce a design methodology that is based on explicit specifications of application graphs and schedules as cooperating dataflow models. We also develop new techniques and tools for automatically synthesizing efficient implementations on multicore platforms from these coupled application and schedule models. We demonstrate the proposed methodology and synthesis techniques through a case study involving real-time detection of people and vehicles using acoustic and seismic sensors.

Energy-Efficient Task Partitioning for Real-Time Scheduling on Multi-Core Platforms

Multi-core processors have become widespread computing engines for recent embedded real-time systems. Efficient task partitioning plays a significant role in real-time computing for achieving higher performance alongside sustaining system correctness and predictability and meeting all hard deadlines. This paper deals with the problem of energy-aware static partitioning of periodic, dependent real-time tasks on a homogenous multi-core platform. Concurrent access of the tasks to shared resources by multiple tasks running on different cores induced a higher blocking time, which increases the worst-case execution time (WCET) of tasks and can cause missing the hard deadlines, consequently resulting in system failure. The proposed blocking-aware-based partitioning (BABP) algorithm aims to reduce the overall energy consumption while avoiding deadline violations. Compared to existing partitioning strategies, the proposed technique achieves more energy-saving. A series of experiments test the capabilities of the suggested algorithm compared to popular heuristics partitioning algorithms. A comparison was made between the most used bin-packing algorithms and the proposed algorithm in terms of energy consumption and system schedulability. Experimental results demonstrate that the designed algorithm outperforms the Worst Fit Decreasing (WFD), Best Fit Decreasing (BFD), and Similarity-Based Partitioning (SBP) algorithms of bin-packing algorithms, reduces the energy consumption of the overall system, and improves schedulability.

Big Data Analytics for Energy Consumption Prediction in Smart Grid Using Genetic Algorithm and Long Short Term Memory

Smart Grids (SG) have smart meters and advance metering infrasturutre (AMI) which generates huge data. This data can be used for predicting energy consumption using big data analytics. A very limited work has been carried out in the literature which shows the utilization of big data in energy consumption prediction. In this paper, the proposed method is based on Genetic Algorithm - Long Short Term Memory (GA-LSTM). LSTM memorises values over an arbitrary interval that manages time series data very effictively while GA is an evolutionary process that is used for optimization. GA combines with LSTM to process hyperparameters such as hidden layers, epochs, data intervals, batchsize and activation functions. Hence, GA creates a new vector for optimum solution that provides minimum error. These methods provide the best performance when compared with existing benchmarks. Moreover, GA-LSTM is used in a multi-threaded environment which increases the speed of convergence. Here, the multi-core platform is operated for solving one-dimensional GA-based inverse scattering problems. The result shows that GA-LSTM provides better convergence as compared to random approach techniques. For validating the results, Pennsylvania-New Jersey-Maryland Interconnection (PJM) energy consumption data has been used while adopting different performance evaluation metrics.