Threshold Voltage Of MOSFET Research Articles

Implementation of homeostasis functionality in neuron circuit using double-gate device for spiking neural network

The homeostatic neuron circuit using a double-gate MOSFET is proposed to imitate a homeostasis functionality of a biological neuron in spiking neural networks (SNN) based on a spike-timing dependent plasticity (STDP). The threshold voltage (Vth) of the double-gate MOSFET is controlled by independent two-gate biases (VG1 and VG2). By using Vth change of the double-gate MOSFET in the neuron circuits, the fire rate of the output neuron is controlled. The homeostasis functionality is implemented by the operation of multi-neuron system based on the proposed neuron circuit. Through the SNN based on STDP using MNIST datasets, it is demonstrated that the recognition rate (~91%) of the SNN with the proposed homeostasis functionality is higher than that (~79%) of the SNN without the proposed homeostasis functionality. Also, the results of the recognition rate with the variations (σ/μ < 0.5) of the synaptic devices and the initial Vth of neuron circuits show a low degradation (1 ~ 3%) in the recognition rate. Thus, it is demonstrated that the homeostasis functionality of the proposed neuron circuit has the immunity to variations (σ/μ < 0.5) of the synaptic devices and the neuron circuits in the SNN based on STDP.

Comparing smoothing techniques for extracting MOSFET threshold voltage

Measurement noise acts as a barrier to the accurate calculation of threshold voltage by derivative-based extraction methods. We examined several smoothing techniques and their effects on measurement noise in threshold voltage extracted by the linear extrapolation method and the gm/Id method. We applied these techniques on a set of SiC power MOSFET devices before and after they had undergone accelerated thermal testing. The smoothing methods examined are least-squares polynomial fitting, low-pass filtering using Butterworth and Chebyshev filters, and differential smoothing. These methods are compared by their shift in threshold voltage compared to unsmoothed data and their standard deviation among the measurements of each device. All methods performed poorly at smoothing when extracting via the gm/Id due to the large amounts of high-magnitude subthreshold noise, mostly tending to extract threshold voltages far below the expected value. Differential smoothing provided results closest to the expected value with an absolute shift of 1.2 V on average. The smoothing methods performed better with the LE method. On a failed device, all smoothing methods except polynomial smoothing preserved the large threshold voltage anomaly for four out of five measurements. These results show that choice of smoothing method, if used must be evaluated based on the device and extraction method.

Ultrathin body nanowire hetero-dielectric stacked asymmetric halo doped junctionless accumulation mode MOSFET for enhanced electrical characteristics and negative bias stability

Abstract This paper presents a 2-D analytical model of ultrathin hetero dielectric, asymmetric halo doped graded channel (HDGC) nanowire junctionless accumulation mode (JAM) MOSFETs obtained by incorporating the concepts of gate-oxide engineering (i.e., hetero dielectric) and channel engineering (i.e., graded channel) simultaneously. Superposition technique with appropriate boundary conditions has been used to solve Poisson's equation for determining the potential distribution function. The minimum central potential concept has been used to derive the threshold voltage of the HDGC-JAM MOSFETs including the quantum confinement effects. The performance of the proposed device has been compared with that of the uniformly doped JAM-MOSFETs. The proposed model also investigates the effect of control and screen gate length variations on short channel effects (SCEs) and hot carrier effects (HCEs) of the proposed device. Further, an analytical total drain current model considering the effects of gate induced drain leakage (GIDL) at negative bias has also been formulated.

Investigating the effect of chirality, oxide thickness, temperature and channel length variation on a threshold voltage of MOSFET, GNRFET, and CNTFET

Investigating the effect of chirality, oxide thickness, temperature and channel length variation on a threshold voltage of MOSFET, GNRFET, and CNTFET

High-Temperature Characterization of a 1.2-kV SiC MOSFET Using Dynamic Short-Circuit Measurement Technique

Threshold voltage and channel mobility of a 1.2-kV planar-channel SiC MOSFET at high junction temperature ( $T_{j}$ ) up to 700 °C have been extracted and analyzed for the first time, by virtue of a specially designed short-circuit (SC) measurement technique we developed. Under the SC condition, $T_{j}$ of the SiC MOSFET can rise significantly within a few microseconds, which can be extracted based on the SC waveforms and thermal calculations. The planar-channel SiC MOSFET investigated in this work can maintain normally-off operation at an elevated $T_{j}$ up to 700 °C. Furthermore, the underlying mechanisms of the temperature dependence of the threshold voltage and channel mobility are also analyzed. The threshold voltage of the SiC MOSFET exhibits a different temperature dependence over a wide range (120–700 °C) compared with that of Si counterparts, which is attributed to interface traps’ response. The channel mobility shows a non-monotonic temperature dependence, due to divergent scattering mechanisms.

SPICE Model Extraction Parameters of Gamma Irradiation on Drain Current and Threshold Voltage of N-Channel MOSFETs

SPICE Model Extraction Parameters of Gamma Irradiation on Drain Current and Threshold Voltage of N-Channel MOSFETs

A Linearity Improved 10-bit 120-MS/s 1.5 mW SAR ADC with High-Speed and Low-Noise Dynamic Comparator Technique

This paper presents a linearity improved 10-bit 120-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with high-speed and low-noise dynamic comparator. A gate cross-coupled technique is introduced in boost sampling switch, the clock feedthrough effect is compensated without extra auxiliary switch and the linearity of sampling switch is enhanced. Further, substrate voltage boost technique is proposed, the absolute values of threshold voltage and equivalent impedances of MOSFETs are both depressed. Consequently, the delay of comparator is also reduced. Moreover, the reduction of threshold voltages for input MOSFETs could bring higher transconductance and lower equivalent input noise. To demonstrate the proposed techniques, a design of SAR ADC is fabricated in 65-nm CMOS technology, consuming 1.5[Formula: see text]mW from 1[Formula: see text]V power supply with a SNDR [Formula: see text][Formula: see text]dB and SFDR [Formula: see text][Formula: see text]dB. The proposed ADC core occupies an active area of 0.021[Formula: see text]mm2, and the corresponding FoM is 24.4 fJ/conversion-step with Nyquist frequency.

Analysis of back-gate effect on threshold voltage of p-channel GaN MOSFETs on polarization-junction substrates

GaN-based p-channel devices using a two-dimensional hole gas are of interest for the realization of GaN CMOS circuits, and threshold voltage control using a back-gate is useful for the circuit design of these devices. In this paper, the back-gate effect on p-channel GaN MOSFETs on polarization-junction substrates is studied. The results show that the obtained dependence of the threshold voltage on the back-gate voltage can be derived by a model equation considering the back surface channel. Also, by comparing the measured characteristics with the simulation result under ideal conditions, it is found that the amount of interfacial charges can be quantitatively evaluated for the fabricated device.

Realization of DTMOS based CFTA and multiple input single output biquadratic filter application

Analog filters can be found in everything from mobile phones to disk drives, from audio systems to power supplies, from telecommunications to broadband internet connection. Analog filters can be formed from a variety of active elements. In this study, the Dynamic Threshold Voltage MOSFET (DTMOS) based Current Follower Transconductance Amplifier (CFTA) active element has been suggested and a multi input single output (MISO) universal biquadratic filter has been obtained with this active element. The proposed circuit operates with ±0.2 V supply voltages and consumes 140 µW power and electronically tunable. All five filtering responses have been realized by selecting the different input signals. All simulations have been performed with LTSpice program using the Predictive Technology Model (PTM) 45 nm Level 54 CMOS process parameters. Analysis of AC/DC, noise, Monte Carlo, temperature, total harmonic distortion (THD) proves that the circuit operates in harmony with the theory. With Monte Carlo analysis, it has been observed that the filter achieves stable output against both passive element and process parameter tolerance. It is hoped that the proposed active element and the filter will be useful in ultra-low voltage, low power, and low frequency analog signal applications.

Modeling of electrical behavior of undoped symmetric Double-Gate (DG) MOSFET using carrier-based approach

PurposeThis study aims to develop a compact analytical models for undoped symmetric double-gate MOSFET based on carrier approach. Double-Gate (DG) MOSFET is a newly emerging device that can potentially further scale down CMOS technology owing to its excellent control of short channel effects, ideal subthreshold slope and free dopant-associated fluctuation effects. DG MOSFET is of two types: the symmetric DG MOSFET with two gates of identical work functions and asymmetric DG MOSFET with two gates of different work functions. To fully exploit the benefits of DG MOSFETs, the body of DG MOSFETs is usually undoped because the undoped body greatly reduces source and drain junction capacitances, which enhances the switching speed. Highly accurate and compact models, which are at the same time computationally efficient, are required for proper modeling of DG MOSFETs.Design/methodology/approachThis paper presents a carrier-based approach to develop a compact analytical model for the channel potential, threshold voltage and drain current of a long channel undoped symmetric DG MOSFETs. The formulation starts from a solution of the 2-D Poisson’s equation in which mobile charge term has been included. The 2-D Poisson’s equation in rectangular coordinate system has been solved by splitting the total potential into long-channel (1-D Poisson’s equation) and short-channel components (remnant 2-D differential equation) in accordance to the device physics. The analytical model of the channel potential has been derived using Boltzmann’s statistics and carrier-based approach.FindingsIt is shown that the metal gate suppresses the center potential more than the poly gate. The threshold voltage increases with increasing metal work function. The results of the proposed models have been validated against the Technology Computer Aided Design simulation results with close agreement.Originality/valueCompact Analytical models for undoped symmetric double gate MOSFETs.

Impact of subthreshold slope on sensitivity of square law detector for high frequency radio wave detection

An impact of subthreshold slope on sensitivity of square law detectors composed of an FET has been investigated. Theoretical consideration starting from the unified charge control model of FET channel carriers comes down to formulae which indicate that the subthreshold slope significantly affects output voltage and sensitivity of the square law detector. Experiments carried out to detect gigahertz waves using a MOSFET which has a body terminal isolated from other terminals and, therefore, is able to operate as the dynamic threshold voltage MOSFET show the significance of the subthreshold slope. Verification performed by detecting terahertz waves using HEMT detectors also proves the theoretical conclusion and almost agrees with detection characteristics predicted from derived mathematical formulae.

Study of oxide trapping in SiC MOSFETs by means of TCAD simulations

SILICON CARBIDE (SiC) material has attracted substantial attention during the last few years as a promising candidate for making power devices for high-temperature operation and under harsh environments. In spite of the considerable progress in device performance, reliability may be a limiting factor for the introduction of SiC MOSFETs in commercial power devices. One of the major reliability concerns is the instability of the threshold voltage in MOSFETs and, similarly, of the flat-band voltage in capacitors under normal operation conditions. This instability is attributed to trapping of channel electrons in interface and bulk oxide traps.The main goal of this work is to investigate how the trapped charges at SiO2/SiC interface influence the C/V curve. In particular, by means of 2-D numerical simulations (SILVACO tools), we could isolate the two different contributions from p-type and n-type doped regions of our MOSFET and we considered both donor and acceptor traps contributions. Then, we compared the simulation results with experimental C/V curves. A good agreement between TCAD simulations and experimental measurements was obtained. So, device simulations can provide a better understanding of such defects at SiO2/SiC interface and we give an insight into the influence of traps, produced during device processing or caused by radiation environment, on the output characteristics of the device.

Threshold voltage and DIBL effect analysis and modeling for FD-SOI MOSFET with high k + SiO$_2$ gate

This study aims to propose a gate structure of high k + SiO$_2$ for a fully depleted silicon-on-Insulator (FD-SOI) MOSFET. We developed a two-dimensional model to calculate its subthreshold surface potential of the front gate, threshold voltage, and drain induced barrier lowering (DIBL) effect. Based on the structure and different dielectric permittivity of FD-SOI MOSFET, the MOSFET of the subthreshold state is divided into several distinct rectangular equivalent sources. Furthermore, two-dimensional (2D) boundary value problems of Poisson and Laplace equations are built on the polygon region. Then, we use the method of separation of variables and the eigenfunction expansion to solve the 2D boundary value problems, and obtained their 2D solutions. Computational results show that the high k + SiO$_2$ gate can effectively suppress the degradation of FD-SOI MOSFET threshold voltage, the aggravation of DIBL effect, and the FIBL effect, which are caused by the dielectric permittivity of high k. Since the equations of the model are linear equations, their computational cost is minimal so that the model can be used for not only modeling and simulation of FD-SOI MOSFETs but also as a device model of circuit simulators.

A 0.6 V 117 nW high performance energy efficient system-on-chip (SoC) CMOS temperature sensor in 0.18 µm CMOS for aerospace applications

This research article presents and describes a novel design with improved performance low power consumption threshold voltage based CMOS thermal sensor for aerospace applications. The proposed temperature sensor utilizes the change in behavior of threshold voltage of MOSFET with variation in temperature. The challenge while designing the temperature sensor was to achieve the linearize output voltage with respect to change in temperature. Process corner analysis has been done to check the robustness of the circuit while performance analysis and sensitivity of the temperature sensor have been verified in the occurrence of parasitic. The proposed temperature sensor is featured with low power consumption, less power supply voltage utilization, high performance and sensitivity with inaccuracy as low as possible. The presented temperature sensor utilizes an active area of 18 µm × 9.85 µm with 117 nW power consumption. An improved linear performance with an inaccuracy of merely − 0.01 to + 0.47 °C over a wide temperature range of − 20 to + 120 °C is presented here. The sensitivity of proposed temperature sensor is found to be as high as 0.77 mV/°C. The proposed temperature sensor is realized and tested in Cadence virtuoso mixed signal design atmosphere using 0.18 µm CMOS technology and further investigated with support of tool from Mentor graphics. The engaged area of pad-limited chip is measured to be 0.96 mm2.

Subthreshold characteristics analysis and modeling of fully depleted silicon-on-insulator MOSFETs with high-k SiO2 stacked gate structure

In this paper, a high-k stacked and SiO2 gate structure is proposed for the fully depleted silicon-on-insulator (FDSOI) MOSFET. We constructed a two-dimensional (2D) model to compute its subthreshold surface potential, threshold voltage, drain-induced barrier lowering (DIBL) effect and fringing-induced barrier lowering (FIBL) effect. Given the structure and wide range of dielectric permittivities of a FDSOI MOSFET, the device in the subthreshold mode is separated into four distinct rectangular equivalent sources, 2D boundary value problems of the Poisson and Laplace equation are built on the polygon region. We used the eigenfunction expansion to solve the 2D boundary value problems and obtain their semianalytical solutions. The computational outcomes demonstrate that the high-k and SiO2 stacked gate structure can suppress the degradation of the FDSOI MOSFET threshold voltage and the aggravation of the DIBL effect. The computational cost of this model is much lesser than traditional models; thus, it can be used for circuit simulators and modeling of FDSOI MOSFETs.

A Study on Electrical Characterization of Surface Potential and Threshold Voltage for Nano Scale FDSOI MOSFET

In this paper the study of electrical characterization of Surface potential &amp; Vth threshold-voltage model is developed for FD SOI MOSFET. The threshold voltage is important parameter in device design. Scaling of device has positive impact on device performance. The various parameters like thickness of silicon film, oxide layer, drain to source voltage plays a key role in improvement of device performance. Surface potential explain the distribution of applied potential throughout the channel. We also analyzed the effect of threshold voltage with various electrical parameters.

Low Substrate Temperature Modeling Outlook of Scaled n-MOSFET

Low substrate/lattice temperature (< 300 K) operation of n-MOSFET has been effectively studied by device research and integration professionals in CMOS logic and analog products from the early 1970s. The author of this book previously composed an e-book in this area where he and his co-authors performed original simulation and modeling work on MOSFET threshold voltage and demonstrated that through efficient manipulation of threshold voltage values at lower substrate temperatures, superior degrees of reduction of subthreshold and off-state leakage current can be implemented in high-density logic and microprocessor chips fabricated in a silicon die. In this book, the author explores other device parameters such as channel inversion carrier mobility and its characteristic evolution as temperature on the die varies from 100‒300 K. Channel mobility affects both on-state drain current and subthreshold drain current and both drain current behaviors at lower temperatures have been modeled accurately and simulated for a 1 𝜇m channel length n-MOSFET. In addition, subthreshold slope which is an indicator of how speedily the device drain current can be switched between near off current and maximum drain current is an important device attribute to model at lower operating substrate temperatures. This book is the first to illustrate the fact that a single subthreshold slope value which is generally reported in textbook plots and research articles, is erroneous and at lower gate voltage below inversion, subthreshold slope value exhibits a variation tendency on applied gate voltage below threshold, i.e., varying depletion layer and vertical field induced surface band bending variations at the MOSFET channel surface. The author also will critically review the state-of-the art effectiveness of certain device architectures presently prevalent in the semiconductor industry below 45 nm node from the perspectives of device physical analysis at lower substrate temperature operating conditions. The book concludes with an emphasis on modeling simulations, inviting the device professionals to meet the performance bottlenecks emanating from inceptives present at these lower temperatures of operation of today's 10 nm device architectures.

Estimation of Threshold Voltage in SiC Short-Channel MOSFETs

In this brief, the influence of high-density traps at the SiO2/SiC interface on short-channel effects was investigated, and a model describing channel length dependence of the threshold voltage (i.e., the gate voltage at a given drain current) is proposed. First, we determined the densities of interface states and fixed charge in 4H-SiC n-channel MOSFET by fitting the calculated gate characteristics to the experimental data, and acquired the density of trapped electrons from the obtained results. Then, we calculated the threshold voltage by considering that the majority of the trapped electrons are emitted near the drain end due to formation of a depletion layer. The channel length dependence of the threshold voltage calculated by the proposed model showed a good agreement with the experimental results even when the definition of threshold voltage was changed. The present model taking account of the fixed charge and of the trapped electron charge enables the estimation of the threshold voltage in the 4H-SiC short-channel MOSFETs.

0.18µm-CMOS Rectifier with Boost-converter and Duty-cycle-control for Energy Harvesting

Existing works on battery-less of energy harvesting systems often assume as a high efficiency of rectifier circuit for power management system. In practice, rectifier circuit often varies with output power and circuit complexity. In this paper, based on a review of existing rectifier circuits for the energy harvesters in the literature, an integrated rectifier with boost converter for output power enhancement and complexity reduction of power management system is implemented through 0.18-micron CMOS process. Based on this topology and technology, low threshold-voltage of MOSFETs is used instead of diodes in order to reduce the power losses of the integrated rectifier circuit. Besides, a single switch with the duty-cycle control is introduced to reduce the complexities of the integrated boost converter. Measurement results show that the realistic performances of the rectifier circuit could be considerably improved based on the performances showed by the existing study.

A Near-Zero-Power Wake-Up Receiver Achieving −69-dBm Sensitivity

This paper presents the design of a wake-up receiver (WuRX) that both improves sensitivity and reduces power over prior art through a multi-faceted design featuring an off-chip impedance transformation network with large passive voltage gain, an active envelope detector with high input impedance to facilitate large passive voltage gain, a low-power precision comparator, and a low-leakage digital baseband correlator. Implemented in a 180-nm silicon on insulator CMOS process using dynamic threshold-voltage MOSFET (DTMOS) devices, the OOK-modulated WuRX operates at 113.5 MHz and achieves a sensitivity of −69 dBm, while consuming just 4.5 nW from a 0.4-V supply.