MOSFET Parasitic Capacitances Research Articles

Influence of MOSFET Parasitic Capacitance on the Operation of Interleaved ZVS Boost Converters

Interleaved zero-voltage switching boost converters have been known for over 20 years. However, the influence of parasitic capacitance of transistors has not been described. In this paper the converter is analyzed and the equation for voltage ratio is derived for any number of converter phases. First a general description of the topology, including main voltage and current waveforms, is provided. Subsequently the converter is analyzed and conditions for soft switching are derived. Next the analysis results are compared to measurements of an experimental converter setup. Discrepancies are identified and the influence of parasitic capacitance is analyzed. By considering the parasitic capacitance the difference between experimental and analytical results of voltage ratio is reduced from 0.2 to less than 0.05.

Improved Performance of CMOS Terahertz Detectors by Reducing MOSFET Parasitic Capacitance

The parasitic circuit elements significantly affect rectification performance of metal-oxide-semiconductor field-effect transistor devices. In this paper, we develop a gate-source parasitic capacitance reduction technique by shifting the source lightly doped drain region and analyze the effectiveness on the improved performance of complementary metal-oxide-semiconductor (CMOS) terahertz (THz) detectors. It is experimentally found that for a 0.65-THz integrated CMOS detector, the maximum improvement of voltage responsivity and noise-equivalent power can be 155% and 70%, respectively, by suppressing the gate-source parasitic capacitance. The device simulation further quantitatively evaluates the gate-source parasitic capacitance under different gate-source overlap areas in the novel fabricated transistor structure. It reveals that a smaller gate-source overlap area can result in a lower gate-source parasitic capacitance, which is more favorable for reducing input THz signal leakage and therefore for increasing the THz responsivity. The works open a wide range of possibilities for the ease of design and fabrication of the high-performance THz detectors in standard CMOS technology.

A zero-voltage-switched three-phase interleaved buck converter

ABSTRACTThis paper proposes a three-phase interleaved buck converter which is composed of three identical paralleled buck converters. The proposed solution has three shunt inductors connected between each other of three basic buck conversion units. With the help of the shunt inductors, the MOSFET parasitic capacitances will resonate to achieve zero-voltage-switching. Furthermore, the decreasing rate of the current through the free-wheeling diodes is limited, and therefore, their reverse-recovery losses can be minimised. The active power switches are controlled by interleaved pulse-width modulation signals to reduce the input and output current ripples. Therefore, the filtering capacitances on the input and output sides can be reduced. The power efficiency is measured to be as high as 98% in experiment with a prototype circuit.

Current mode single-input multi-output MOSFET-only filter

In this paper, a very simple topology of a current mode MOSFET-only filter with single-input and multi-output is proposed. It is very important to emphasize that it is possible to obtain five of the filter functions, namely low-pass (LP), band-pass (BP), high-pass (HP), band-stop (BS) and all-pass (AP) using the proposed topology without using external passive elements. The core circuit of the proposed filter employs only four MOS transistors; therefore, it occupies very small chip area. It is also possible to adjust the filter gain with the biasing voltage. In addition, the circuit exhibits a very low input impedance and also high output impedances which make it possible for cascading. The MOSFET capacitances which determine the transfer functions are all grounded, so physical capacitances can be used instead of MOSFET parasitic capacitances to operate the filter at very low frequencies. Moreover, proposed filter structure has low supply voltage as 1V in order to be applicable to low voltage operations. Detailed simulation results, including noise and Monte Carlo analysis, are provided using 0.18µm TSMC technology parameters to verify the feasibility of the filter circuit.

A Class-E Power Amplifier Design Considering MOSFET Nonlinear Drain-to-Source and Nonlinear Gate-to-Drain Capacitances at Any Grading Coefficient

This paper presents theory and analysis for class-E power amplifier considering MOSFET nonlinear gate-to-drain and nonlinear drain-to-source capacitances at any grading coefficient of the MOSFET body junction diode. The nonlinearity degree of a MOSFET parasitic capacitance is determined by the grading coefficient. When the grading coefficient is not considered in design procedure, the switch voltage waveform of the class-E power amplifier does not satisfy the switching conditions, which results in a decrease of the power conversion efficiency. Therefore, the grading coefficient is an important parameter to satisfy the class-E zero-voltage switching (ZVS) and zero-derivative switching (ZDS) conditions. The MOSFET gate-to-drain capacitance is highly nonlinear, and it is more nonlinear than drain-to-source capacitance for most MOSFETs. In some cases, the change in the gate-to-drain capacitance can be as large as 100 times. The results show that this nonlinearity affects the class-E power amplifier properties, such as switch voltage, power output capability, and maximum switch voltage. Therefore, it is necessary to consider the nonlinearity of the gate-to-drain capacitance, along with the drain-to-source capacitance. A design example at 4 MHz operating frequency is also given to describe the design procedure. The ZVS and ZDS conditions are achieved in the obtained switch voltage. The circuit simulation was performed using PSpice software. For verification of the presented theory, a class-E power amplifier is fabricated. The measured results are verified with simulation and theory results.

Refined Conformal Mapping Model for MOSFET Parasitic Capacitances Based on Elliptic Integrals

In this paper, the main MOSFET parasitic capacitances of planar devices (i.e., bulk, Fully depleted silicon-on-insulator (FDSOI), and planar double gate) are computed using two successive conformal mapping transforms. First, the structure is mapped to the real axis of the complex plane, and then the second transform, deduced directly from the Schwarz-Christoffel theorem, reduces the capacitance to the trivial parallel electrodes case. This second step involves elliptic integrals, which provide a generic expression for all parasitic capacitances. This method is later compared against other models based on conformal mapping. Finally, the results are validated with finite-element method simulations of the inner and outer fringe capacitances in different architectures, including metallic contacts and raised and faceted junctions.

Analysis and Design of Class-E Power Amplifier With MOSFET Parasitic Linear and Nonlinear Capacitances at Any Duty Ratio

This paper presents analytical expressions for the class-E power amplifier with MOSFET linear gate-to-drain and nonlinear drain-to-source parasitic capacitances at any duty ratio. The maximum operating frequency, output power capability, and element values as functions of the duty ratio are obtained. The element values are directly dependent upon the selection of duty ratio and require a careful duty ratio selection to minimize component power losses and to maximize the total efficiency. Two design examples at 25 and 9 W output power at 4-MHz operating frequency along with the PSpice-simulation and experimental waveforms are presented. It is shown from the derived expressions that the slope of the voltage across the MOSFET gate-to-drain parasitic capacitance during the switch-off state as a function of the duty ratio affects the switch-voltage waveform. Therefore, it is possible to achieve the required peak switch voltage and the class-E ZVS/ZVDS conditions simultaneously by adjusting the duty ratio. The theoretical results and PSpice simulations agreed with experimental results quantitatively, which shows the validity of the presented analysis.

ENERGY CAPACITY OF A VOLTAGE-DEPENDENT CAPACITOR FOR THE CALCULATION OF MOSFET's SWITCHING LOSS

Energy capacity of a voltage-dependent capacitor is investigated and defined. An equation for the calculation of energy capacity of the MOSFET's parasitic capacitance is formulated. The defined energy capacity of a voltage-dependent capacitance can be used to calculate switching loss of resonant switches by simply calculating the energy transferred into or retrieved from the MOSFET. The validity of the proposed formula is verified by computer simulation. The discrepancy between energy capacity of the MOSFET's parasitic capacitance calculated from the formulated equation and that calculated from the results of computer simulation is negligible. Computer simulation is also used to validate the proposed switching-loss calculation technique.

Characterization and Experimental Assessment of the Effects of Parasitic Elements on the MOSFET Switching Performance

This paper presents a comprehensive study on the influences of parasitic elements on the MOSFET switching performance. A circuit-level analytical model that takes MOSFET parasitic capacitances and inductances, circuit stray inductances, and reverse current of the freewheeling diode into consideration is given to evaluate the MOSFET switching characteristics. The equations derived for emulating MOSFET switching transients are assessed graphically, which, compared to results obtained merely from simulation or parametric study, can offer better insight into where the changes in switching performance lie when the parasitic elements are varied. The analysis has been successfully substantiated by the experimental results of a 400 V, 6 A test bench. A discussion on the physical meanings behind these parasitic effect phenomena is included. Knowledge about the effects of parasitic elements on the switching behavior serves as an important basis for the design guidelines of fast switching power converters.

An Investigation Into the Effects of the Gate Drive Resistance on the Losses of the MOSFET–Snubber–Diode Configuration

This paper presents an investigation into the effects of the gate drive resistance on the losses of the MOSFET–snubber–diode (MSD) configuration commonly used in many power converters. An analytical loss model that takes the circuit stray inductances, MOSFET parasitic capacitances and inductances, and reverse current characteristic of the freewheeling diode into consideration is derived to describe the interactions among the MOSFET, snubber, and freewheeling diode during the switching transients. Two possible turn-ON switching situations, determined by the gate drive part and the power part, respectively, are distinguished in the analysis. It is then used to study the effects of the stray inductances, gate drive resistance and snubber on the switching behaviors, power loss distribution, and voltage stress on the MOSFET in the entire MSD configuration. A sequence of steps will be given to illustrate how an optimal combination of the gate drive resistance and snubber capacitance is determined, in order to minimize the overall loss of the MSD configuration for a maximum permissible voltage stress on the MOSFET. The loss model and method of determining the gate drive resistance and snubber capacitance are evaluated by comparing the theoretical predictions with the experimental results of a 400V, 6A test bench. The performances of the MSD configuration with different types of freewheeling diodes will be studied.

Analysis and Design Method for High-Frequency Self-Oscillating Electronic Ballasts

In this paper, the analysis and design methodology of a high-frequency self-oscillating (SO) electronic ballast with lamp current control are presented. SO electronic ballasts have two important drawbacks: First, the lamp current varies according to the ac input voltage, causing undesired effects in the lamp brightness, and second, the design method lacks precision at very high frequency operation (greater than 200 kHz) mainly due to the parasitic capacitance. The ballast is modeled by using the descriptive function method and the extended Nyquist criterion; the model of the ballast includes a control circuit and takes into account the high-frequency effect of the MOSFET parasitic capacitance. Finally, experimental results of a 38-W SO electronic ballast prototype with lamp current control for high-intensity discharge lamps are presented to validate the analysis and the proposed methodology. The switching frequency is selected at 2 MHz in order to avoid the acoustic resonance problem.

A New Three-Dimensional Capacitor Model for Accurate Simulation of Parasitic Capacitances in Nanoscale MOSFETs

A new 3-D gate capacitor model is developed to accurately calculate the parasitic capacitances of nanoscale CMOS devices. The dependences on gate length and width, gate electrode and dielectric thicknesses, gate-to-contact spacing, and contact dimension and geometry are fully incorporated in this model. The accuracy is certified by an excellent match with the 3-D interconnection simulation results for three structures with strip, square, and circular contacts. The features of being free from fitting parameters and proven accuracy over various geometries make this model useful for nanoscale MOSFET parasitic capacitance simulation and analysis. Furthermore, the developed capacitor model in the form of multidimensional integral can easily be deployed in general circuit simulators. This model predicts that the parasitic capacitance <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">of</sub> dominates around 25% of the intrinsic gate capacitance ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gint</sub> ) in 80-nm MOSFETs and that the near nonscalability with gate length brings the weighting factor <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">of</sub> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gint</sub> above 30%/40%/60% in 65-/45-/32-nm devices. It actually exceeds the limitation defined by the most updated ITRS and reveals itself as a show-stopper in high-speed and high-frequency circuit design.

전원 잡음 영향을 줄이기 위한 VCO 정전압기 분석

정전압기는 VCO의 제어전압의 전원 잡음을 줄이기 위해 사용될 수 있다. 정 전압기의 최적 설계를 위해선 정전압기에 대한 정확한 해석이 필요하다. 본 논문에서는 최근 발표된 논문의 정전압기 해석 과정에 MOSFET의 기생 커패시턴스 성분을 고려하지 않은 문제점을 보완하였다. 이 문제점을 이론적으로 분석하여 정확한 해석을 유도하였고, 회로 시뮬레이션과 측정을 통해 검증하였다. 정전압기는 <TEX>$0.18{\mu}m$</TEX> 1P6M CMOS 공정으로 설계되었고, 칩 면적은 <TEX>$1mm^2$</TEX> 이다. A voltage regulator can be used to reduce the effect of the power-supply noise on the control voltage of the VCO. An accurate analysis of the voltage regulator circuit is needed for the optimal design of the voltage regulator. This paper clarifies an inaccuracy in a recent paper on the replica-compensated regulator far supply-regulated PLLs: neglect of MOSFET parasitic capacitances. As a consequence, an improved analytical model is derived for the replica-compensated voltage regulator. The derived model is verified through circuit simulation. The voltage regulator has been fabricated in a standard <TEX>$0.18{\mu}m$</TEX> 1P6M CMOS technology. The chip area is <TEX>$1mm^2$</TEX>.

Modeling of MOSFET parasitic capacitances, and their impact on circuit performance

We study layout dependent, parasitic capacitance contributions of MOSFETs with 3D simulations, and show that these contributions are for narrow and short devices comparable to intrinsic contributions. The performance of 65-nm technology is strongly affected by these components, and should therefore be modeled accurately in circuit simulations. We propose a methodology how to accurately and consistently model them in a design flow. The methodology is validated with ring oscillator measurements.

Linear and nonlinear modeling of switched-capacitor ΔΣ modulators

A new methodology is presented for both linear and nonlinear circuit-level modeling of switched-capacitor ΔΣ modulators. It takes account of the MOSFET parasitic capacitances, switch on-resistances, opamp gain-bandwidth products, the nonlinear behavior of the parasitic capacitances and opamps, clock jitter, etc. Mathematically, a system of circuit equations is constructed by nodal analysis in the frequency domain, and its solutions in the form of Volterra series are mapped into the time domain by numerical Laplace inversion. The methodology can be used for nonlinear-distortion analysis. It is implemented in software within MATLAB.

Ultra-Compact High-Linearity High-Power Fully Integrated DC–20-GHz 0.18-$\mu{\hbox {m}}$ CMOS T/R Switch

A fully integrated ultra-broadband transmit/receive (T/R) switch has been developed using nMOS transistors with a deep n-well in a standard 0.18-mum CMOS process, and demonstrates unprecedented insertion loss, isolation, power handling, and linearity. The new CMOS T/R switch exploits patterned-ground-shield on-chip inductors together with MOSFET's parasitic capacitances to synthesize artificial transmission lines, which result in low insertion loss over an extremely wide bandwidth. Negative bias to the bulk or positive bias to the drain of the MOSFET devices with floating bulk is used to reduce effects of the parasitic diodes, leading to enhanced linearity and power handling for the switch. Within dc-10, 10-18, and 18-20 GHz, the developed CMOS T/R switch exhibits insertion loss of less than 0.7, 1.0, and 2.5 dB and isolation between 32-60, 25-32, and 25-27 dB, respectively. The measured 1-dB power compression point and input third-order intercept point reach as high as 26.2 and 41 dBm, respectively. The new CMOS T/R switch has a die area of only 230 mumtimes250 mum. The achieved ultra-broadband performance and high power-handling capability, approaching those achieved in GaAs-based T/R switches, along with the full-integration ability confirm the usefulness of switches in CMOS technology, and demonstrate their great potential for many broadband CMOS radar and communication applications

A new technique of cancelation of the MOSFET leakage currents and parasitic capacitances

Abstract The paper presents a new topological technique to be used with MOSFET's to appreciably minimize their channel and drain leakage currents (by a factor of 4) and parasitic capacitances (about 10 times smaller). It also enhances the channel inversion rate due to the channel potential distribution and leads consequently to greater device-switching speeds (10 times greater). This technique will allow a smaller device to device separation without fearing from any proximity effects. It is based on the creation of a transverse lateral field which is oriented so as to keep the channel electrons within its potential-well and to reduce the channel to substrate depletion layer width. A detailed study and characterization of the new technique is comprised.