Abstract
정전압기는 VCO의 제어전압의 전원 잡음을 줄이기 위해 사용될 수 있다. 정 전압기의 최적 설계를 위해선 정전압기에 대한 정확한 해석이 필요하다. 본 논문에서는 최근 발표된 논문의 정전압기 해석 과정에 MOSFET의 기생 커패시턴스 성분을 고려하지 않은 문제점을 보완하였다. 이 문제점을 이론적으로 분석하여 정확한 해석을 유도하였고, 회로 시뮬레이션과 측정을 통해 검증하였다. 정전압기는 <TEX>$0.18{\mu}m$</TEX> 1P6M CMOS 공정으로 설계되었고, 칩 면적은 <TEX>$1mm^2$</TEX> 이다. A voltage regulator can be used to reduce the effect of the power-supply noise on the control voltage of the VCO. An accurate analysis of the voltage regulator circuit is needed for the optimal design of the voltage regulator. This paper clarifies an inaccuracy in a recent paper on the replica-compensated regulator far supply-regulated PLLs: neglect of MOSFET parasitic capacitances. As a consequence, an improved analytical model is derived for the replica-compensated voltage regulator. The derived model is verified through circuit simulation. The voltage regulator has been fabricated in a standard <TEX>$0.18{\mu}m$</TEX> 1P6M CMOS technology. The chip area is <TEX>$1mm^2$</TEX>.
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