Abstract
We study layout dependent, parasitic capacitance contributions of MOSFETs with 3D simulations, and show that these contributions are for narrow and short devices comparable to intrinsic contributions. The performance of 65-nm technology is strongly affected by these components, and should therefore be modeled accurately in circuit simulations. We propose a methodology how to accurately and consistently model them in a design flow. The methodology is validated with ring oscillator measurements.
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