MOS Devices Research Articles

Exploring the influence of Al content on the optical and interface properties of HfAlOx mixed gate dielectric thin films and their applications in MOS devices

Exploring the influence of Al content on the optical and interface properties of HfAlOx mixed gate dielectric thin films and their applications in MOS devices

Selective Epitaxy of Tensile, Highly Doped SiP for Planar NMOS FD-SOI Devices

The epitaxy of sources and drains is a critical enabler for enhanced transistor performances. In N-type MOS devices, selective SiP epitaxy can simultaneously yield (i) very high levels of electrically active dopants which is crucial for contact resistance minimization and (ii), tensile strain in Raised Sources and Drains (RSD) on each side of Si FD-SOI channels. This study present process solutions in order to benefit from large amounts of phosphorus in a silicon lattice and have thereby tensile strain, while maintaining excellent crystal quality, good surface morphology and a low electrical resistivity. We use here industrial precursors widely used in manufacturing, e.g. a [SiH2Cl2 + PH3 + HCl + H2] chemistry, for the selective deposition, in the 600°C-700°C range, of SiP in conventional epitaxy reactors. We achieved phosphorous concentrations as high as 4.6×10²¹ cm-3 (9.3%) in blanket SiP layers while preserving good crystal quality. In FD-SOI devices, we succeeded in having a selective process yielding rather smooth and free of defects Si:P films with 1.6×10²¹ cm-3(3.2%) of P.

Structural design and electronic performance at MOx/diamond (M = Hf, Zr, Ti, Al, Sc, Y) interfaces for MOS device applications

The ultra-wide bandgap semiconductor diamond represents a promising potential for advancement and innovation in the field of electronic device development. Utilizing first-principles calculations, a thorough investigation has been performed on the structural and electronic characteristics of MOx/diamond (MOx = HfO2, ZrO2, TiO2, Al2O3, Sc2O3, Y2O3) heterostructures. The concentration of charge transfer at the high-κ oxide/diamond interfaces leads to obvious interface polarity localization characteristics. The studied MOx/diamond heterojunctions feature insulating interfaces without any gap states. The MOx/diamond supercells exhibit the ability to effectively confine holes on the diamond surface owing to the large band offsets (>1 eV), showing typical electronic properties of “type II” staggered energy band configurations. These findings demonstrate that the high-κ oxide MOx/diamond can serve as highly promising diamond gate dielectrics, and provide theoretical insights into the interfacial engineering of diamond MOS devices.

Design Optimization of a THz Receiver Based on 60 nm Complementary Metal–Oxide–Semiconductor Technology

The technology transfer of terahertz wireless communication from research laboratories to commercial applications is a global strategic achievement currently pursued to match the ever-increasing demand for high-speed communication. The use of commercial integrated electronics for the detection of THz waves is an intriguing challenge which has enticed great interest in the scientific research community. Rapid progress in this field has led to the exploitation of THz direct detection using standard CMOS technology based on the so-called self-mixing effect. Our research, stemming out of a collaboration between Sapienza University of Rome and STMicroelectronics company, is focused on the complete design process of a THz rectifier, realized using 50 nm ST B55 CMOS technology. In this paper, we report the optimization process of a case-study receiver, aimed to demonstrate the feasibility of direct demodulation of the transmitted OOK signal. A relatively limited bandwidth extension is considered since the device will be included in a system adopting a radiation source with a limited band. The design refers to a specific technology, the 60 nm MOS in B55X ST; nevertheless, the proposed optimization procedure can be applied in principle to any MOS device. Several aspects of the rectification process and of the receiver design are investigated by combining different numerical simulation methodologies. The direct representation of the rectification effect through the equivalent circuit of the detector is provided, which allows for the investigation of the detector–amplifier coupling, and the computation of output noise equivalent power. Numerical results are presented and used as the basis for the optimization of the receiver parameters.

Si/ZnO:Coumarin photocapacitor for electro and photonic applications

The present study first investigated the photocapacitance measurements of Al/p-Si/ZnO:Coumarin/Au metal-oxide-semiconductor MOS device at room temperature in the frequency range of 10 kHz-1MHz and bias voltage range of −5 V; +5 V. Based on photocapacitance analysis, Vbi, Na, Nss, Ef, Em, Δϕb, ϕb, Wd values were calculated for 10 kHz, 100 kHz and 1 MHz. For 1 MHz, Vbi value was 0.79 eV, Na value was 3.54x1015 cm−3, ϕb value was 0.99 eV and Wd value was 530 nm. Additionally, the dielectric constant (ε′), dielectric loss (ε″), electrical modulus (M′M″) and complex impedance (Z*), tangent loss (tanδ), ac conductivity(σac) and phase angle (φ) values of the device were also calculated. ε′ values were calculated 116 at 10 kHz, 58 at 100 kHz and 6 at 1 MHz. These ε′values indicate that the higher ZnO:Coumarin layer can store more charge carriers. This study has shown that materials produced by ZnO, a metal oxide semiconductor, doped with coumarin have the potential to be used in many optoelectronic devices, especially in photonic applications.

An investigation of 60Co gamma radiation induced damage in N-channel MOSFETS at cryogenic temperature.

N-channel depletion metal oxide semiconductor field effect transistors (MOSFETs) were irradiated with 60Co gamma radiation in the dose range of 100 krad to 6Mrad at cryogenic (77K) and room temperatures (300K). The MOS devices irradiated at 77K and 300K were characterized at 77K and 300K respectively. The different electrical parameters of MOSFET such as threshold voltage (Vth), density of interface trapped charges (ΔNit), density of oxide trapped charges (ΔNot) and mobility of the charge carriers (μ) were studied as a function of total dose. A considerable increase in ΔNit and ΔNot and decrease in Vth was observed after irradiation. The 77K irradiation results were then compared with 300K irradiation results and found that the degradation in the electrical characteristics is more for the devices irradiated at 300K.

Assessment of 180 nm double SOI technology for analog front-end design with back-gate voltage

This paper provides an assessment of the electrical and noise performance in the 180 nm double silicon-on-insulator (DSOI) technology, which shows advantages for analog front-end radiation detectors. For the first time, the impact of the back-gate voltage on the electrical and noise performance of DSOI MOSFETs is investigated. The transconductance-to-current (gm /ID ) ratio and low-frequency (1/f) noise were measured as a function of the MOS device types (NMOS/PMOS), gate length, and bias condition of front- and back-gates. Experimental results show that positive back-gate voltage deteriorates the gm /ID ratio of the MOSFETs in weak inversion region. The DSOI NMOS devices overwhelm the PMOS with better gm /ID and 1/f performance. The DSOI devices have a comparable 1/f noise with the 180 nm SOI counterparts. With negative back-gate voltage applied, the low frequency noise performance of NMOS is improved. This assessment of DSOI technology gives a guideline for the readout circuit design in detector front-end systems.

Novel layout technique for single-event transient mitigation by the groove structure

Based on the damage mechanism of single-event transient (SET) in a MOS device, a new irradiated reinforcement uniaxial strained Si Nano NMOSFET device is further proposed, and the new structure device has no effect on the electrical properties of its original structure. Moreover, the new reinforced device of groove structure can efficiently reduce not only charge collection but also SET pulse widths (WSET). Compared with the conventional NMOS and drain-wall structure, we find that the proposed novel layout technique can provide the best benefit of SET mitigation with a small sacrifice in the effective area. Therefore, the successful development of the research results will play a positive role in promoting the theoretical and technological progress of high-performance radiation-resistant core electronic components and lay a foundation and create conditions for their application in space radiation and nuclear radiation.

Impact of Oxide Charges on The Minority Carrier Response in MOS(p) Devices With Al2O3/SiO2 Gate Stacks under Strong Inversion Condition

In this study, a compact model proposed in the previous work (2) was utilized to elucidate an unusual minority carrier response time observed in MOS(p) devices with Al2O3/SiO2 gate stacks. It is supposed that the number of oxide charges increases with SiO2 thickness. The findings confirmed the heightened sensitivity of device alternating current (AC) characteristics to oxide charges in the outer region. Accordingly, we explored the dependencies of oxide thickness and quality on the transition frequency (ωm) of devices.

Theoretical Insight into the Band Alignment at High-κ Oxide XO2/Diamond (X = Hf and Zr) Interfaces with a SiO2 Interlayer for MOS Devices.

Diamond has become a promising candidate for high-power devices based on its ultrawide bandgap and excellent thermoelectric properties, where an appropriate gate dielectric has been a bottleneck hindering the development of diamond devices. Herein, we have systematically investigated the structural arrangement and electronic properties of diamond/high-κ oxide (HfO2, ZrO2) heterojunctions by first-principles calculations with a SiO2 interlayer. Charge analysis reveals that the C-Si bonding interface attracts a large amount of charge concentrated at the diamond interface, indicating the potential for the formation of a 2D hole gas (2DHG). The diamond/HfO2 and diamond/ZrO2 heterostructures exhibit similar "Type II" band alignments with VBOs of 2.47 and 2.21 eV, respectively, which is consistent with experimental predictions. The introduction of a SiO2 dielectric layer into the diamond/SiO2/high-κ stacks exhibits the typical "Type I″ straddling band offsets (BOs). In addition, the wide bandgap SiO2 interlayer keeps the valence band maximum (VBM) and conduction band minimum (CBM) in the stacks away from those of diamond, effectively confining the electrons and holes in MOS devices. This work exhibits the potential of SiO2/high-κ oxide gate dielectrics for diamond devices and provides theoretical insights into the rational design of high-quality gate dielectrics for diamond-based MOS device applications.

Theoretical study of the influence of GaOx interfacial layer on the GaN/SiO2 interface property

The spontaneous formation of a Ga-oxide (GaOx) intermediate layer at the GaN/SiO2 interface has been reported during the SiO2 deposition on the GaN substrate. In this study, we have performed first-principles calculations and unveiled atomic and electronic structures of the GaN/SiO2 interface with 1-nm thick GaOx intermediate layer. Our calculations show that the top-layer Ga atoms on the GaN side are terminated with the O atoms on the GaOx side, leading to the clean GaN/GaOx interface and the absence of the electronic state in the midgap region. However, strongly localized states, which are originated from O atoms lone-pair orbitals in the –GaOSi– local structures, emerge in the gap near the valence-band maximum of GaN. These in-gap states become hole traps in GaN MOS devices, leading to a degradation in device controllability and operational speed.

Effects of Interface Traps and Hydrogen on the Low-Frequency Noise of Irradiated MOS Devices

Effects of Interface Traps and Hydrogen on the Low-Frequency Noise of Irradiated MOS Devices

Er‐Doped MgAl2O4 Nanofilms Enabling Highly Efficient Near‐Infrared Electroluminescence from the Silicon‐Based MOS Devices Fabricated by Atomic Layer Deposition

AbstractEr3+‐doped polycrystalline MgAl2O4 (MAO:Er) spinel nanofilms are deposited via atomic layer deposition, and the metal‐oxide–semiconductor light emitting devices are fabricated. The crystallinity and morphology of the MAO:Er nanofilms are explored by modifying the annealing temperatures, Al2O3/MgO ratios and Er2O3 dopant cycles. The similar electroluminescence (EL) emissions peaking at 1530 nm indicates the identical crystal field environment for the doped Er3+ ions. The concentration quenching is verified to occurs via the energy transfer among the neighboring Er3+ ions. The optimal device (800 °C‐annealed, Al2O3/MgO ratio close to stoichiometry, Er3+: 1.85 mol%) yields the highest external quantum efficiency of 28%, the power efficiency of 0.32% and the optical power density of 14.62 mW cm−2. The smooth MAO:Er spinel nanofilms with the low refractive index and high resistance ensure the highly efficient light extraction and the generation of energetic electrons for the impact excitation of Er3+ ions. The trap‐assisted tunneling under operation electric field dominates the conduction mechanism for the EL emissions. The estimated decay lifetime of 1154.4 µs and a large‐stimulated emission cross‐section in the order of 10−15–10−14 cm2 are revealed from the EL emissions. Intense near‐infrared emissions from these Si‐based MAO:Er devices have great potential in the optoelectronic applications.

A new analytical method for modeling a 2D electrostatic potential in MOS devices, applicable to compact modeling

This paper presents a new conformal mapping method to solve 2D Laplace and Poisson equations in MOS devices. More specifically, it consists of an analytical solution of the 2D Laplace equation in a rectangular domain with Dirichlet boundary conditions, with arbitrary values on the boundaries. The advantages of the new method are that all four edges of the rectangle are taken into account and the solution consists of closed-form analytical expressions, which make it fast and suitable for compact modeling. The new model was validated against other similar methods. It was found that the new model is much faster, easier to implement, and avoids many numerical issues, especially near the boundaries, at the cost of a very small loss in accuracy.

Lowering of interface state density between deposited gate oxide and SiC substrate via controlling substrate oxidation

The quality of oxide/semiconductor interface in SiC gate stacks is engineered by employing atomic layer deposition of gate oxide and controlling post-deposition annealing (PDA) under the vacuum. We find that the interface state density (Dit) can be substantially lowered by reducing the thickness of thermally formed SiO2 between the deposited gate dielectric and SiC in PDA. In addition, Dit slightly far from the conduction band is further reduced by avoiding low temperature SiC oxidation and that near the conduction band is reduced by controlling suboxide formation. These results provide new insights into improving the interface performance of SiC MOS devices.

Electronic properties of ZrO2 films fabricated via atomic layer deposition on 4H-SiC and Si substrates

Being an important semiconductor material for high power applications, silicon carbide (SiC) faces the problems while used as a gate oxygen layer in traditional Si MOS devices. In view of this, an innovative approach was adopted in the present work to replace the conventional SiO2 with a high-k material (ZrO2) as the gate oxygen layer to investigate its effect on the electrical characteristics of the devices. In particular ZrO2 films were deposited on Si and SiC substrates by atomic layer deposition (ALD), and Al was used as the electrode. The atomic force microscopy (AFM) microregion scan revealed a highly flat surface with Rq < 1 nm after the ALD growth of ZrO2 layer. The sample surface analysis via x-ray photoelectron spectroscopy (XPS) suggested the presence of a small amount of ZrOx components. According to the electron energy loss spectrum (EELS), the band gap width (Eg) of this ALD ZrO2 dielectric was 5.45 eV, which met the requirements for high-quality 4H-SiC-related MOS devices. The electrical properties of the samples were then studied, and the maximum breakdown voltage of the Al/ZrO2/SiC/Al MOS structure was obtained to be 23 V, i.e., nearly twice that of the Si substrate. As for the oxide layer, the interface defect density (Dit) near the conduction band of the Al/ZrO2/SiC/Al MOS structure was only 1012 eV−1 cm−2 orders of magnitude. The Neff value (the movable charge) of the structure was also controlled at 1012 cm−2. Therefore, the overall performance of the ZrO2/SiC structure in terms of electrical properties exceeded that of the ZrO2/Si structure and previously reported counterparts. In this respect, the ZrO2/SiC MOS capacitor structure has great research potential.

A Comprehensive Review of Single Event Transients on Various MOS Devices

A Comprehensive Review of Single Event Transients on Various MOS Devices

Investigation of Low Energy Electron Irradiated SiO2 Based MOS Devices by Capacitance-Voltage and Thermally Stimulated Current Techniques

Investigation of Low Energy Electron Irradiated SiO2 Based MOS Devices by Capacitance-Voltage and Thermally Stimulated Current Techniques

A low-power low-noise amplifier with high CMRR for wearable healthcare applications

Low-noise and low-power operation are important parameters of amplifier intended for wearable healthcare applications. However, along with these parameters the amplifier must be able to deliver high Common Mode Rejection Ratio (CMRR) for mitigating the effect of 50/60 Hz interference. This paper reports capacitively coupled-capacitive feedback amplifier based on Self Cascode Current Mirror-II (SCCM-II) Operational Transconductance Amplifier (OTA). The obtained results for proposed SCCM-II OTA based amplifier shows gain of 39.79 dB, input referred noise of 2.64 μVrms, bandwidth of 0.794-343.4 Hz, area consumption of 0.154 μm2, power consumption of 2.54 μW with ±0.9 V supply. The noise efficiency factor and CMRR values for proposed amplifier are 3.87 and 122.1 dB, respectively. In-depth theoretical interpretations and mathematical modeling of amplifier are validated in 0.18μm standard CMOS process using BSIM3V3 MOS device models. The Gaussian distribution plots of proposed amplifier for 200 Monte-Carlo iterations infer mean values for gain and CMRR are 39.79 dB and 112.96 dB which are very close to their nominal values. The proposed amplifier has been compared with conventional approach as well as with literature and improvement in results is observed in terms of input referred noise, power and CMMR. These advantages of the proposed amplifier make it suitable for non-invasive wearable healthcare applications.

Digital-logic assessment of junctionless twin gate trench channel (JL-TGTC) MOSFET for memory circuit applications

In this paper, Junctionless Twin Gate Trench Channel (JL-TGTC) MOSFET with individual gate control is realized. The device gives full functionality of 2-input digital ‘AND’ and ‘NAND’ logics. The simulation depicts the results in the form of various parameters such as cutoff current, transfer characteristics, and potential profiles. All the simulations regarding device structure and functionality are done on TCAD. This new type of MOS device has improved applicability in low-voltage digital electronics such as sequential circuits etc.