MOS Current Mode Logic Research Articles

Variation Aware Design of 50-Gbit/s, 5.027-fJ/bit Serializer Using Latency Combined Mux-Dual Latch for Inter-Chip Communication

The conventional MOS current mode logic (MCML)-based multiplexer needed for serializer application has various limitations, such as low voltage-swing, substantial power consumption, and large area overhead. In the circuit arrangement of a serializer using the MCML-based mux-tree concept, the output of one mux at any stage is used to feed another mux at the next stage through some latch circuits, which are basically used for timing synchronization giving away penalty in terms of delay and area. The increase in number of stages of the Serializer may lead to further reduction in output swing (if common mode is not properly set), thereby causing signal integrity issues and finally loss of data. To address the same, a latency combined current mode multiplexer incorporating pMOS-based dual cross-coupled latch circuit is unearthed in this paper to further outline an area and energy efficient high-speed serializer capable of maintaining uniform peak-to-peak swing and signal quality at differential outputs. The simulations of new serializer are performed for 90-nm CMOS in the Cadence Virtuoso platform, where the average power and delay are found to be $471.6~\mu \text{W}$ and 93.9 ps, respectively, to provide a power delay product of 43.8 fJ only at a power supply of 1 V. An improved output swing of 904 mV is also noticed along with a data rate of 50 Gb/s and a BER of <10−12. The entire design is proved to be a robust one after simulating it through Monte Carlo at five different process corners and also validated at lower process nodes such as 28-nm UMC.

An energy efficient PVT aware novel CML-TG based Mux-Latch circuit Serializes high rate data

The high speed wireline communication suffers from a lot of signal quality issues such as jitter and swing, which eventually leads to higher probability of data loss. As the current mode multiplexer, being the integral cell of any transceiver circuit guides to Serialize data in high rate, its arrangement is of utmost importance. This work explores a novel configuration of multiplexer embedded with cross-coupled NMOS latch after integrating the Transmission Gate (TG) principle with the MOS Current Mode Logic (MCML). The proposed configuration reads an average power, delay and power-delay product (PDP) of as tiny as 135.7 μW, 20.16 ps and 2.736 fJ, respectively when simulated for 90 nm CMOS using Cadence Virtuoso at 10 GHz switching frequency and 1 V power supply. The process variation is performed at different corners through Monte-Carlo runs with ‘no skew’ and ‘5% process skew’ variation at both pre-layout and post-layout to prove the robustness of the proposed Mux-Latch, which is employed to tender a new low gate count and energy efficient variation aware Serializer circuit capable of offering a data rate of as high as 50 Gbit/s. The entire circuit is also validated at lower technology nodes like 28 nm UMC.

Design and development of high performance MOS current mode logic (MCML) processor for fast and power efficient computing

Power dissipation and delay product have emerged to be crucial issue, which prove to decrease the performance of microprocessor. The MOS current mode logic (MCML) is an evolving logic family that is attracting interest owing to its high speed operation, reliable performance in comparison to the CMOS logic family. However, the MCML suffers from constant static power dissipation, which, if left unmanaged, would result in an inordinate energy requirement in large scale ICs. In order to resolve this challenge, the newly introduced system designed a modified MOS current mode logic (modified MCML) that has remarkable characteristics of lesser power dissipation, better switching frequency and greater processing speed. With the aim of achieving low power dissipation, the dynamic MOS current mode logic (dynamic MCML) is proposed. Dynamic MCML circuits integrate the benefits of MCML circuits with those that of the dynamic logic families for achieving great performance using a low-supply voltage along with low-power dissipation. The results obtained from simulation show that the newly introduced design model of dynamic MCML yields greater power conservation and higher processing speed in comparison with conventional CMOS technology, MCML and modified MCML with regard to power dissipation and power delay product.

Design of Low Voltage D-Flip Flop Using MOS Current Mode Logic (MCML) For High Frequency Applications with EDA Tool

Design of Low Voltage D-Flip Flop Using MOS Current Mode Logic (MCML) For High Frequency Applications with EDA Tool

A low-power 6-bit MOS CML flash ADC with a novel multi-segment encoder for UWB applications

This paper introduces a novel structure of multi-segment encoder with MOS current mode logic (MCML) multiplexers. As the benefit, the more segments would lead higher performance speed. Moreover, in the high-resolution flash analog-to-digital converter (ADC), the encoder structure will be simpler compared to conventional ones. As the simplest type, the two-segment encoder is used in this paper. By assistance of some MCML multiplexers, each segment encodes the most significant bits (MSBs) and the least significant bits (LSBs) separately. The figure of merit (FOM) of the proposed ADC is 0.225pJ/conversion-step.

New Proposal for MCML Based Three-Input Logic Implementation

This paper presents a new proposal for three-input logic function implementation in MOS current mode logic (MCML) style. The conventional realization of such logic employs three levels of stacked source-coupled transistor pairs. It puts restriction on minimum power supply requirement and results in increased static power. The new proposal presents a circuit element named as quad-tail cell which reduces number of stacked source-coupled transistor levels by two. A three-input exclusive-OR (XOR) gate, a vital element in digital system design, is chosen to elaborate the approach. Its behavior is analyzed and SPICE simulations using TSMC 180 nm CMOS technology parameters are included to support the theoretical concept. The performance of the proposed circuit is compared with its counterparts based on CMOS complementary pass transistor logic, conventional MCML, and cascading of existing two input tripple-tail XOR cells and applying triple-tail concept in conventional MCML topology. It is found that the proposed XOR gate performs best in terms of most of the performance parameters. The sensitivity of the proposed XOR gate towards process variation shows a variation of 1.54 between the best and worst case. As an extension, a realization of 4 : 1 multiplexer has also been included.

MOS current mode logic exclusive-OR gate using multi-threshold triple-tail cells

This paper presents a modified low-voltage MOS current mode logic (MCML) exclusive-OR (XOR) gate. The proposed topology introduces multiple threshold voltage transistors in the triple-tail cell of a MCML XOR gate. This scheme allows reduction in the implementation area of a triple-tail cell and the logic gate employing it. The impact of employing multiple threshold voltage transistors on the operation of the XOR gate is investigated; and mathematical formulations for the static and delay parameters are derived. A design procedure based on the static model is put forward. The accuracy of the models is verified by designing and simulating the proposed XOR gate for wide operating conditions. The model parameters of TSMC 0.18µm CMOS technology are used. An assessment in terms of implementation area and the process variations is conducted for the proposed and the available XOR gates. Finally, the performance of all the XOR topologies is compared for different design cases and the favorable cases are identified.

Current-mode circuit-level technique to design variation-aware nanoscale summing circuit for ultra-low power applications

Prodigious demand for fast performance-ultra low power electronic devices has insinuated the discovery of circuit style that promises reduced propagation delay (t p ), as well as low power dissipation (PWR). MOS current mode logic (MCML) style has emerged as a promising logic style that offers high speed of operation at the expense of acceptable power dissipation. This paper proposes a MCML full adder which employs a load controller circuit. It compares MCML full adder with hybrid-CMOS full adder in terms of various design metrics in superthreshold as well as subthreshold regions. MCML topology with load controller offers a high speed of operation and low power dissipation in superthreshold region. Same circuit arrangement, when operated in subthreshold region also delivers higher operating speed with ultralow power dissipation compared to its hybrid-CMOS counterpart. Power dissipation analysis established MCML based full adder more robust compared to its hybrid-CMOS counterpart. In particular, MCML full adder design achieves 3.77× (2.38×) improvement in propagation delay, 10.43× (3.45×) improvement in average power dissipation, 39.43× (8.21×) lower power-delay product (PDP) and 149.07× (19.55×) improvement in energy-delay product (EDP) in superthreshold (subthreshold) regions of operation at 16-nm technology node. The above results are also validated using TSMC’s industry standard 0.18-μm technology model parameters and a similar trend is observed in the design metrics of the MCML and hybrid-CMOS full adder circuits. In addition, noise performance of the above mentioned circuits is also carried out. It is observed that the noise induced by the hybrid-CMOS full adder is about 14× to that of the MCML full adder.

Back to the Future: Current-Mode Processor in the Era of Deeply Scaled CMOS

This paper explores the use of MOS current-mode logic (MCML) as a fast and low noise alternative to static CMOS circuits in microprocessors, thereby improving the performance, energy efficiency, and signal integrity of future computer systems. The power and ground noise generated by an MCML circuit is typically 10– $100 \times $ smaller than the noise generated by a static CMOS circuit. Unlike static CMOS, whose dominant dynamic power is proportional to the frequency, MCML circuits dissipate a constant power independent of clock frequency. Although these traits make MCML highly energy efficient when operating at high speeds, the constant static power of MCML poses a challenge for a microarchitecture that operates at the modest clock rate and with a low activity factor. To address this challenge, a single-core microarchitecture for MCML is explored that exploits the $C$ -slow retiming technique, and operates at a high frequency with low complexity to save energy. This design principle contrasts with the contemporary multicore design paradigm for static CMOS that relies on a large number of gates operating in parallel at the modest speeds. The proposed architecture generates 10– $40\times $ lower power and ground noise, and operates within 13% of the performance (i.e., 1/ExecutionTime) of a conventional, eight-core static CMOS processor while exhibiting $1.6\times $ lower energy and 9% less area. Moreover, the operation of an MCML processor is robust under both systematic and random variations in transistor threshold voltage and effective channel length.

Design of Filter Using MOS Current Mode Logic Logic

MCML (MOS Current Mode Logic) is a method used for the purpose of reducing the delay and power of the circuit. In high speed application this method is used to reduce the power. In this method the sleep transistor is inserted in series with the supply voltage (or) current source to reduce the power. Different power gating techniques are been used to reduce the static power and to improve the speed and efficiency of the circuit. In this paper, the filter can be designed by using MCML logic. Here we are introducing the fourth order band pass filter by using MCML logic. In order to reduce the power and delay this method is proposed.

Design of Filter Using MOS Current Mode Logic

MCML (MOS Current Mode Logic) is a method used for the purpose of reducing the delay and power of the circuit. In high speed application this method is used to reduce the power. In this method the sleep transistor is inserted in series with the supply voltage (or) current source to reduce the power. Different power gating techniques are been used to reduce the static power and to improve the speed and efficiency of the circuit. In this paper, the filter can be designed by using MCML logic. The fourth order band pass filter by using MCML logic is introduced. In order to reduce the power and delay this method is proposed.

Improved tri-state buffer in MOS current mode logic and its application

This paper presents a new topology to implement MOS current mode logic (MCML) tri-state buffer. The current source section of the available MCML tri-state buffer is modified in the proposed topology which improves output enable time and maintains the low power feature. The functionality of the proposed topology is verified through SPICE simulations by using 0.18 µm TSMC CMOS technology parameters. Its performance is compared with the available one for different values of bias current ranging from 50 to 200 µA. The delay decreases with increase in current and improvement in output enable time is visible throughout the current range. The impact of parameter variations at different design corners and width mismatch on the performance of both the proposed and the available tri-state buffers is also studied and similar variations are found. The significance of the improvement is demonstrated through the implementation of a tri-state buffer based edge triggered register, a key element in digital systems design.

Comparative Analysis of Universal Gates using MCML and CMOS Technique

MOS current mode logic (MCML) is an emerging logic family which is gaining attention due to its high speed of operation, robust performance and presence of mere switching noise as compared to the CMOS logic family. In this paper we have compared universal gates using MCML and conventional CMOS in terms of power and propagation delay at 16-nm Technology node. Comparative analysis shows that MCML universal gates has less power and delay as compared to conventional CMOS based universal gates at 16 nm technology. Variability analysis establishes MCML based universal gates as the most resilient and immune to various electrical parameters.

Illustrative Comparison of MCML and CMOS Design Techniques using Tanner EDA

In this paper, a comparison is done between MOS Current Mode Logic (MCML) and Complementary metal Oxide Semiconductor (CMOS) circuits operating in low power application. It is found that MCML logic circuits exhibit a decrease in delay and so decrease in overall power delay product compared with CMOS circuits. The tested inverter are optimized for low power and high-speed operation, according to the simulation of the circuits for lower voltage. This simulation is done using Tanner EDA. From the results shown it is seen that the MCML logic circuits reveal high efficiency and good performance at low power and high speeds which makes them to be more capable for application in the integrated circuits with high density.

A Power-Gating Scheme for MCML Circuits with Separable-Sizing Sleep Transistors

Power-efficient designs are essential for micro-power sensor systems. This paper presents a power-gating scheme for MCML (MOS Current Mode Logic) circuits with separable-sizing sleep transistors. In the proposed scheme, two high-threshold power-gating transistors are inserted between load transistors and outputs of the MCML circuits. The widths and lengths of sleep transistors in power-gated blocks are separately adjusted, which are independent of the bias circuit. Basic cells and a 1-bit full adder are used to verify the correctness of the proposed scheme. The power consuming comparisons between conventional MCML and proposed power-gating MCML circuits are carried out. The 1-bit MCML full adder based on the proposed scheme nearly saves 36% of energy dissipations with respect to no-power-gating MCML one, for a power-gating activity of 0.6. Moreover, the proposed power-gating MCML circuit also has a great advantage in power dissipations in high frequency regions compared with the power-gating static CMOS ones. The power consumption of the MCML 1-bit full adder based on the proposed scheme is 63.2%, 44.8%, and 36.97% compared with the powergating static CMOS one when the operating frequency is 1GHz, 1.5GHz, and 2GHz, respectively.

Modeling and Sizing of Power-Gating Single-Rail MOS Current Mode Logic

Almost all power-gating circuits used in MOS current-mode circuits were realized with dual-rail schemes. In this paper, a power-gating scheme for single-rail MOS current mode logic (SRMCML) is presented. The modeling of the sleep transistor in power-gating circuits is constructed and analyzed. The optimization methods for sizing sleep transistors of power-gating circuits are addressed in terms of energy dissipations. The design methods of the power-gating SRMCML circuits are presented. The effectiveness of the proposed power-gating structure is verified by using HSPICE simulations with a SMIC 130nm technology. From the outcomes of simulations, the energy loss of the power-gating SRMCML circuits is smaller than corresponding static CMOS alternatives in high frequencies.

Power-Gating Single-Rail MOS Current-Mode Logic Circuits Using High- Threshold PMOS Transistors as Linear Resistors

In this paper, a power-gating technology for single-rail MOS Current Mode Logic (SRMCML) circuits is pre- sented, which use the high-threshold PMOS transistors as linear load resistors to reduce the power dissipation in the sleep mode. The basic SRMCML cells, such as buffer/inverter, AND2/NAND2, AND3/NAND3, OR2/NOR2, OR3/NOR3, XOR2/XNOR2, multiplexer, and 1-bit full adder, are used to verify the effectiveness of the proposed power-gating scheme. The equivalent model for calculating energy dissipations of the power-gating SRMCML circuits is constructed. All circuits are simulated with HSPICE at a 130 nm CMOS process. By simulating power-gating SRMCML circuits in active and sleep modes, it is concluded that the power dissipation of power-gating SRMCML circuits in sleep mode is reduced with the decrease of the device sizes of high-threshold PMOS sleep transistors, while the power dissipation of power-gating SRMCML circuits is almost independent of the device sizes of sleep transistors in active mode. The power dissipation comparisons among power-gating SRMCML, conventional SRMCML, and power-gating static CMOS circuits are carried out. The power dissipation of the proposed power-gating SRMCML circuits is the least among the three above mentioned structures.

Diseño de una biblioteca de compuertas MCML utilizando un algoritmo genético y optimización multiobjetivo

&lt;p class="p1"&gt;En este documento se alude al problema de dimensionamiento de circuitos MCML (&lt;em&gt;MOS Current Mode Logic&lt;/em&gt;). Se introduce el Frente de Pareto como una herramienta de análisis útil para explorar el espacio de diseño de las distintas compuertas que conforman nuestra biblioteca básica MCML. Un algoritmo genético (GA) es implementado para detectar automáticamente este frente, en un proceso que busca eficientemente las parametrizaciones óptimas del diseño y sus correspondientes valores en un espacio de aptitudes. Las mediciones del consumo de potencia, el retardo de propagación y el rango del voltaje de salida se usan como funciones de aptitud, puesto que el problema se trata como una tarea de optimización multiobjetiva. Finalmente, se presentan los resultados de las simulaciones &lt;em&gt;postlayout&lt;/em&gt;, usando la tecnología de fabricación AMS 0,35 μm. &lt;/p&gt;

Power Optimized Transceivers for Future Switched Networks

Network equipment power consumption is under increased scrutiny. To understand and decompose transceiver power consumption, we have created a toolkit incorporating a library of transceiver circuits in 45-nm CMOS and MOS current mode logic (MCML) and characterize power consumption using representative network traffic traces with digital synthesis and SPICE tools. Our toolkit includes all the components required to construct a library of different transceivers: line coding, frame alignment, channel bonding, serialization and deserialization, clock-data recovery, and clock generation. For optical transceivers, we show that photonic components and front end drivers only consume a small fraction (<;22%) of total serial transceiver power. This implies that major reductions in optical transceiver power can only be obtained by paying attention to the physical layer circuits such as clock recovery and serial-parallel conversions. We propose a burst-mode physical layer protocol suitable for optically switched links that retains the beneficial transmission characteristics of 8b/10b, but, even without power gating and voltage controlled oscillator power optimization, reduces the power consumption during idle periods by 29% compared with a conventional 8b/10b transceiver. We have made the toolkit available to the community at large in the hope of stimulating work in this field.

Dynamic Current Mode Logic Realization of Digital Arithmetic Circuits

In this paper, we realize a high performance arithmetic circuits which is faster and have lower power consumption using a new dynamic logic family of CMOS and to analyze its performance for arithmetic circuits. This new dynamic logic family is known as Dynamic Current Mode Logic (DyCML). DyCML circuits combine the advantages of MOS current mode logic (MCML) circuits with those of dynamic logic families to achieve high performance at a low-supply voltage with low-power dissipation. A major advantage of the DyCML is the dynamic current source, which achieves smaller delays compared to the basic MCML circuits. Other advantages inherited from MCML are high performance and robustness to supply voltage scaling. DyCML gates reduce power dissipation by reducing the output voltage swing. We compare a set of arithmetic circuits implemented in Dynamic Current Mode Logic with the other dynamic logic styles. Simulation and test results show that DyCML circuits are superior to DDCVS logic styles in terms of power dissipation. A 2-bit multiplier, full adder & xor/xnor gate in DyCML style is fabricated in 180nm CMOS technology. 2-bit multiplier and a full adder dissipate 145.1 µW and 55.14 µW respectively at 40 MHz for a voltage swing of 1.2V in DyCML style.