Moore's Law Research Articles

First Observation of Negative Capacitance in Molecular Ferroelectric Thin Films.

On the path of persisting Moore's Law, one of the biggest obstacles is the "Boltzmann tyranny," which defines the lower limit of power consumption of individual transistors. Negative capacitance (NC) in ferroelectrics could provide a solution and has garnered significant attention in the fields of nanoelectronics, materials science, and solid-state physics. Molecular ferroelectrics, as an integral part of ferroelectrics, have developed rapidly in terms of both performance and functionality, with their inherent advantages such as easy fabrication, mechanical flexibility, low processing temperature, and structural tunability. However, studies on the NC in molecular ferroelectrics are limited. In this study, the focus is centered on the fabricated high-quality thin films of trimethylchloromethyl ammonium trichlorocadmium(II), and a pioneering investigation on their NC responses is conducted. The findings demonstrate that the NC exhibited by molecular ferroelectrics is comparable to that of conventional HfO2 -based ferroelectrics. This underscores the potential of molecular material systems for next-generation electronic devices.

Resistive Switching Effect in Ag‐poly(ethylene Glycol) Nanofluids: Novel Avenue Toward Neuromorphic Materials

AbstractConventional computation techniques face challenges of deviations in Moore's law and the high‐power consumption of data‐centric computation tasks. Neuromorphic engineering attempts to overcome these issues by taking inspiration from neuron assemblies, ranging from distributed synaptic plasticity through orchestration of oscillator‐like action potential toward avalanche dynamics. Although solid networks of nanoparticles (NPs) are proven to replicate fingerprints of criticality and brain‐like dynamics, the aspect of dynamic spatial reconfigurations in the connectivity of networks remains unexplored. In this work, Ag/poly(ethylene glycol) (PEG) nanofluids are demonstrated as potential systems to mimic the spatio‐temporal reconfiguration of network connections. The nanofluids are prepared by directly loading Ag NPs from the gas aggregation cluster source into liquid PEG. The NPs exhibit a negative zeta potential in PEG; if the potential difference is applied between two electrodes submerged in this nanofluid, the NPs migrate toward the anode, accumulate in its vicinity, and form a conductive path. Spikes of electric current passing through the path are detected, accompanied by resistive switching phenomena, similar to the random switching dynamics in solid NPs networks. The unique behavior of Ag/PEG nanofluids makes them promising for the realization of spatio‐temporal reconfigurations in network topologies with the potential to transition to 3D.

Prediction of intel CPUs price with regression analysis

CPU stands for the central processing unit. It is a unit that executes the instruction and allows the computer to run programs, making it an essential computer component. When people are looking for a new computer, either buying a built one or building one, CPU takes up a significant portion of the computer budget. The existence of Moores Law indicates that the CPUs price is predictable. This essay constructed the two models, multinomial linear regression and multivariable polynomial regression models, based on parts of Intel CPUs parameter value to predict their recommended sale price. According to the data set used in this research and the built model, the multinomial linear regression model is more accurate in predicting.

Ni Single-Atoms Based Memristors with Ultrafast Speed and Ultralong Data Retention.

Memristor with low-power, high density, and scalability fulfills the requirements of the applications of the new computing system beyond Moore's law. However, there are still nonideal device characteristics observed in the memristor to be solved. The important observation is that retention and speed are correlated parameters of memristor with trade off against each other. The delicately modulating distribution and trapping level of defects in electron migration-based memristor is expected to provide a compromise method to address the contradictory issue of improving both switching speed and retention capability. Here, high-performance memristor based on the structure of ITO/Ni single-atoms (NiSAs/N-C)/Polyvinyl pyrrolidone (PVP)/Au is reported. By utilizing well-distributed trapping sites , small tunneling barriers/distance and high charging energy, the memristor with an ultrafast switching speed of 100ns, ultralong retention capability of 106 s, a low set voltage (Vset ) of ≈0.7V, a substantial ON/OFF ration of 103 , and low spatial variation in cycle-to-cycle (500 cycles) and device-to-device characteristics (128 devices) is demonstrated. On the premise of preserving the strengths of a fast switching speed, this memristor exhibits ultralong retention capability comparable to the commercialized flash memory. Finally, a memristor ratioed logic-based combinational memristor array to realize the one-bit full adder is further implemented.

Raman scattering monitoring of thin film materials for atomic layer etching/deposition in the nano-semiconductor process integration

According to Moore's law, the semiconductor industry is experiencing certain challenges in terms of adapting to highly sophisticated integrated technology. Therefore, controlling materials at the atomic scale is considered a mandatory requirement for further development. To this end, atomic layer deposition and etching skills are being increasingly researched as potential solutions. However, several considerations exist for adopting atomic technology with respect to surface analysis. This review primarily focuses on the use of Raman scattering for evaluating atomic-layered materials. Raman scattering analysis is expected to gradually expand as a semiconductor process and mass-production monitoring technology. As this can enhance the applications of this method, our review can form the basis for establishing Raman scattering analysis as a new trend for atomic-scale monitoring.

Characterization of the electrical properties of an optical device manufactured with CMOS 0.35 μm technology

<p>Currently, the relevance of optical devices has increased due to the physical limitations of the electrical transmission medium and the proximity of the limit of Moore's Law. Furthermore, the fabrication of optical devices on monolithic silicon substrates has gained importance in recent years thanks to manufacturing technologies in the microelectronics industry. For this reason, this paper aims to carry out the electrical characterization of an optical device manufactured with commercial austria micro syste m technology of complementary metal oxide semiconductors of 0.35 μm. The methodology consists of implementing an optical device, with an incandescent optical source called a microlamp, a waveguide and a photodiode. The microlamp was projected between two m etal layers connected by tungsten vias that act as filaments covered by SiO 2 dielectric to prevent oxidation. The results of the electrical characterization of the optical device show that the microlamp reaches a maximum current of 48 mA and stops working at higher currents. The waveguide was designed with a SiO 2 core and it was discovered that the TiN layers were found to be part of the waveguide causing it to behave as an emitter in the 2.5 - 5 <em>µ</em>m region.</p>

Modeling Of 3D Integrated Circuits, Heat Transfer Solutions and Application

As transistor sizes approach the quantum limit, the cost of further shrinking them becomes prohibitively high. To overcome this limitation and surpass Moore's Law, 3D (Integrated Circuits) IC technology has emerged. However, while 3D ICs offer advantages like high integration, they also present challenges related to thermal management. This paper introduces and discusses partial differential equations and modeling methods for heat transfer in 3D ICs. It explores solutions to address thermal conduction problems and analyzes the potential application areas and prospects of 3D ICs. By utilizing different modeling methods, we can optimize the heat transfer problem during the design stage. To enhance the thermal conduction of 3D ICs, this study proposes the use of copper thermal conductive materials, graphene thermal conductive layers, and phase-change material cooling. As technology advances and costs decrease, 3D ICs are expected to find broader applications in high-performance computing, artificial intelligence, the Internet of Things, and other fields. Despite its numerous advantages, 3D integrated circuit technology still faces challenges such as cost, heat, and silicon vias. To address these issues, further technological innovations and updates to Computer Aided Design (CAD) tools are necessary. Overall, this study holds significant social and scientific importance as it promotes the development of 3D IC technology, improves electronic device performance, and advances scientific research.

Comparison and analysis of gate dielectrics for SiC MOSFET

SiC MOSFET has been widely used for its characteristics of lower on-off resistance, less switching loss, higher working frequency, and high-temperature resistance. With the scale down of Moore's Law, better gate dielectrics should be selected to improve the breakdown voltage and reduce the gate-drain current to ensure a good working mode of MOSFETs. The traditional gate dielectric is SiO2 but their dielectric constant is low and the interface characteristics at the junction of SiO2 and SiC are poor so various emerging materials have been created to replace the traditional SiO2. Emerging gate dielectrics such as high-k gate dielectrics are receiving a lot of attention today, they can increase breakdown voltage and decrease gate-drain current while maintaining oxide thickness. Among many emerging gate dielectrics, Al2O3, HfO2, and HfSiON have been noticed due to their good characteristics and a lot of research on them. This paper will focus on the analysis of the characteristics of these three materials and their applications in MOSFET. Finally, after a detailed analysis of the three materials, they three materials are compared to understand their differences.

Quantum-Inspired Digital Annealing for Join Ordering

Finding the optimal join order (JO) is one of the most important problems in query optimisation, and has been extensively considered in research and practise. As it involves huge search spaces, approximation approaches and heuristics are commonly used, which explore a reduced solution space at the cost of solution quality. To explore even large JO search spaces, we may consider special-purpose software, such as mixed-integer linear programming (MILP) solvers, which have successfully solved JO problems. However, even mature solvers cannot overcome the limitations of conventional hardware prompted by the end of Moore's law. We consider quantum-inspired digital annealing hardware, which takes inspiration from quantum processing units (QPUs). Unlike QPUs, which likely remain limited in size and reliability in the near and mid-term future, the digital annealer (DA) can solve large instances of mathematically encoded optimisation problems today. We derive a novel, native encoding for the JO problem tailored to this class of machines that substantially improves over known MILP and quantum-based encodings, and reduces encoding size over the state-of-the-art. By augmenting the computation with a novel readout method, we derive valid join orders for each solution obtained by the (probabilistically operating) DA. Most importantly and despite an extremely large solution space, our approach scales to practically relevant dimensions of around 50 relations and improves result quality over conventionally employed approaches, adding a novel alternative to solving the long-standing JO problem.

Two-dimensional van der Waals ferroelectric field-effect transistors toward nonvolatile memory and neuromorphic computing

With the gradual decline in Moore's law, traditional silicon-based technologies have encountered numerous challenges and limitations, prompting researchers to seek solutions. Two-dimensional (2D) van der Waals (vdWs) ferroelectric (Fe) field-effect transistors (FETs) (2D vdWs FeFETs) are devices that integrate emerging 2D vdWs ferroelectric materials into the transistor structures. In comparison with traditional complementary metal oxide semiconductor FETs (COMSFETs), they exhibit superior performance, including lower power consumption, higher switching speed, and improved stability. The vdWs FeFETs are anticipated to surpass the limits imposed by Moore's law, offering increased possibilities and opportunities for research and application in the field of nanoelectronics, particularly in nonvolatile memory (NVM) and neuromorphic computing (NMC). In this review, we summarize the recent research progress of vdWs FeFETs and elucidate their development origin, basic structure, and working mechanism. Furthermore, we explore the application of vdWs FeFETs in NVM, NMC, and large-scale arrays. Finally, we highlight the prominent challenges and future directions in this field.

Toward a Voltage Reconfigurable Logic Gate

Currently, novel approaches are being developed to overcome the imminent Moore's law failure. The techniques attempt to gain greater computing power by reducing the number of transistors. This work presents the simulation of a reconfigurable voltage logic gate based on the equation of a plane. The proposal is achieved by using two variables of the equation of a plane as inputs and the other as output. The proposed circuit can perform the NAND and NOR logic gates, known as universal logic gates. The simulation results show the feasibility of the proposed reconfigurable logic gate. Also, the presented circuit is compatible with the transistor-transistor-logic and can be modified to implement other logic gates by changing a voltage level.

Nonvolatile Memory Organic Light-Emitting Transistors.

In the field of active-matrix organic light emitting display (AMOLED), large-size and ultra-high-definition AMOLED applications have escalated the demand for the integration density of driver chips. However, as Moore's Law approaches the limit, the traditional technology of improving integration density that relies on scaling down device dimension is facing a huge challenge. Thus, developing a multifunctional and highly integrated device is a promising route for improving the integration density of pixel circuits. Here, a novel nonvolatile memory ferroelectric organic light-emitting transistor (Fe-OLET) device which integrates the switching capability, light-emitting capability and nonvolatile memory function into a single device is reported. The nonvolatile memory function of Fe-OLET is achieved through the remnant polarization property of ferroelectric polymer, enabling the device to maintain light emission at zero gate bias. The reliable nonvolatile memory operations are also demonstrated. The proof-of-concept device optimized through interfacial modification approach exhibits 20 times improved field-effect mobility and five times increased luminance. The integration of nonvolatile memory, switching and light-emitting capabilities within Fe-OLET provides a promising internal-storage-driving paradigm, thus creating a new pathway for deploying storage capacitor-free circuitry to improve the pixel aperture ratio and the integration density of circuits toward the on-chip advanced display applications.

The development history and future trends of the microchip

This essay provides a detailed analysis of the evolution of microchip technology from its inception to its prospects. It starts by discussing the foundational work of pioneers like Jack Kilby and Robert Noyce and the transformative effect of Moore's Law on chip design and manufacturing. It then evaluates the current state of chip technology, including the leading industry players and challenges such as chip shortages and trade disputes. The essay then explores the anticipated trends in chip technology, such as quantum computing and innovative materials like graphene. It concludes by assessing the expected influence of these advancements on various sectors, including Artificial Intelligence (AI), the Internet of Things (IoT), and autonomous vehicles, and their broader social, economic, and environmental implications. This essay presents a comprehensive and thoughtful analysis of microchip technology's past, present, and future and its far-reaching impact on modern society.

Finite element modeling and analysis method for predicting and optimizing the warpage of construction before flip chip bonding in System-on-Wafer process flow

As one of the solutions to surpass the limitations of Moore's Law in the post-Moore era, System-on-Wafer (SoW) technology provides the capability to integrate multiple chip components onto a single silicon wafer. A new high-density integrated SoW solution is discussed in this article. However, significant warpage can result from mismatches in the coefficients of thermal expansion (CTE) of different materials in a 12-in. wafer, presenting considerable challenges for the flip chip (FC) bonding, installation of power delivery and heat dissipation systems. Severe warpage can directly lead to the failure of the entire system. Therefore, pre-assessment and optimization of the warpage are crucial. This paper proposes a multi-scale modeling approach to assess the wafer warpage prior to FC bonding in the SoW fabrication process. To evaluate the accuracy of the modeling approach, a dummy die to thinned wafer and molding (DDTWM) was first designed and fabricated. The sole distinction in fabrication process between DDTWM and SoW is the absence of through silicon via (TSV) and backend of line (BEOL) metal traces. The simulation and experiment for DDTWM achieve a good level of consistency. In addition, following the completion of warpage simulations on the actual SoW structure prior to FC bonding, utilizing the same modeling approach, we proceeded to perform a Response Surface Methodology (RSM) analysis on several crucial parameters that exert influence on warpage. Subsequent to analyzing the results, optimization simulations were executed, underscoring the significant instructive value of RSM analysis in optimizing warpage within the structure prior to FC bonding in the SoW manufacturing process. This work offers an effective solution for predicting and mitigating substrate warpage prior to FC bonding in the SoW fabrication process, contributing to comprehensive warpage control.

Equilibrium phase diagram design and structural optimization of SAC/Sn-Pb composite structure solder joint for preferable stress distribution

The Package-on-Package (PoP) technology is an efficient knowhow to increase the efficiency of electronic components, hence to secure the continuation of the validity of Moore's law. This novel form of packaging technology with bottom stackable narrow pitch Ball Grid Array (BGA) contributes to the integrity of the package. However, the high solder joint density introduces a great challenge on the packaging reliability. Therefore, more stringent requirements must be put forward for achieving the increased performance. That can be achieved by using composite solder joints. In this study, a novel composite SAC (Sn-3Ag-0.5Cu)/Sn-Pb (Sn37Pb) solder joint was designed for improving the stress distribution and its overall mechanical integrity. The formation process and a phase distribution of composite solder joint were investigated, indicating that the phase distribution mainly depends on the reflow temperature. The dissolution ratio of SAC into the composite solder at different temperatures was estimated by the phase diagram. The predicted values were consistent with the experimental results. A review of mechanical property test results, the best performance solder joint could be obtained at 200 °C for the dwell time of 60 s if the composite includes 10 wt% SnPb. The stress distribution of composite solder joint was analyzed by finite element simulation. By actively concentrating the stress in the middle area of the solder joint, the maximum stress in the composite solder reduced for up to 29% when compared to full SAC solder joint.

Treehouse: A Case For Carbon-Aware Datacenter Software

The end of Dennard scaling and the slowing of Moore's Law has put the energy use of datacenters on an unsustainable path. Datacenters are already a significant fraction of worldwide electricity use, with application demand scaling at a rapid rate. We argue that substantial reductions in the carbon intensity of datacenter computing are possible with a software-centric approach: by making energy and carbon visible to application developers on a fine-grained basis, by modifying system APIs to make it possible to make informed trade offs between performance and carbon emissions, and by raising the level of application programming to allow for flexible use of more energy efficient means of compute and storage. We also lay out a research agenda for systems software to reduce the carbon footprint of datacenter computing.

Fabrication of low-dimensional superparamagnetic vanadium diselenide clusters for expanding magnetic storage capacity

The chip performance has been improving with the process technology in recent years following the Moore's law. Their applications and necessities are in various fields such as 5G communications, Internet of Things (IoT), mining cryptocurrency and Neural network computing (NNC) for artificial intelligence (AI). However, when the processing signals are emitted from processing units and finally transferred to memories, the transferring speed is decreasing. Therefore, among all the novel research of memories, it is anticipated to develop the technology with high storage capacity and enough processing performance. From previous literature of Intel published in 2020, the technology with those characteristics is determined as warm memory. During the following years, the most distinctive technology is MRAM which utilizes magnetic materials as core technology breaking the component frame of using electric materials and impacting the developing direction of memory. But among the development of MRAM in recent years, the significant difficulties are the competition between magnetic anisotropy energy and heat in micro-size range resulting in the transition from superparamagnetism to ferromagnetism confining the smallest size in component development for MRAM. So the novel solution is utilizing the transition metal dichalcogenides (TMDs) in order to produce low dimensional applications of spintronic thin films. In this report, we utilize the TMD material, VSe2 which is firstly published as a process recipe of self-assembled zero dimensional (0D) superparamagnetic clusters. In addition, a novel mechanism called expanding magnetic technology (ExM tech.) is demonstrated by superparamagnetic VSe2/ferromagnetic Co interfaces. The 0D superparamagnetic clusters are successfully synthesized on the surface of ferromagnetic thin films. The direction of magnetization for those superparamagnetic clusters will transform from random alignment to the specific alignment along with the magnetization direction of the ferromagnetic thin films which is attributed to the pinning from the ferromagnetic thin films. Therefore, the total magnetization of magnetic thin films can be significantly enhanced in size range of angstrom by ExM tech. After million cycles of reliability examinations, the magnetic properties remain stable. This technology will be beneficial for the applications on component process which can reach the expected total magnetizations with smaller size of magnetic thin films in MRAM. Those research results give MRAM as a nvRAM great potential on the commercial production.

Moore's Law: The potential, limits, and breakthroughs

Moore's Law is a concept that notes the doubling of the number of transistors on a microchip around every two years, resulting in exponential advancement in computing power and diminishing costs. However, as transistor sizes have approached the physical limits of silicon-based technology, maintaining this pace of growth has become increasingly challenging. As a result, researchers have been exploring alternative solutions, such as System-in-package(SiP), Chiplets, Non-volatile memory, Biocomputing, quantum computing, and photonics. While these technologies are still in the early stages of development, they offer promising solutions to the challenges facing the continued growth of computing power. As we continue to explore new avenues for technological advancement, we may find that Moore's Law continues to hold true in unexpected and exciting ways.

Neuromorphic behaviors of VO2 memristor-based neurons

Neuromorphic computing has the potential to overcome the limitations of the von Neumann Bottleneck and Moore's Law. Memristors, characterized by nanoscale, adjustable resistance, low power consumption, and non-volatility, are considered as one of the best candidates for neuromorphic computing. This paper utilizes an accurate model of VO2 locally active memristor fabricated by HRL Labs to construct second-order and third-order neuronal circuits, which can exhibit 21 different types of neuromorphic behaviors. These behaviors include all or nothing firing, complex spiking, bursting, refractory period, accommodation, chaos, and others. Based on the theories of local activity and the Edge of Chaos (EoC), this paper analyzes the dynamics of the neuronal circuits, demonstrating the biological neurons operate at the EoC, and the neuromorphic behaviors emerge on or near the EoC, which reveals the generation mechanism of the action potential.

Open-source, multi-layer LSI design & fabrication framework for distributed IP development and education

Continuous development of Large Scale Integration (LSI) technologies based on Moore's law results in highly developed LSI technologies, as well as very high costs in design and fabrication and high design complexity. This fact prevents various users from contributing to the activities of designing LSIs, fabricating LSIs, and developing Intellectual Properties (IPs). On the other hand, the trend towards open-source has been attracting attention to overcome these problems and extend the potential of LSI technologies. The purpose of this research is to develop an open-source LSI design framework aimed at connecting various layers of LSI knowledge. Its methodology is composed of two parts. One is the development of the LSI design flow using existing open-source EDA tools and their related glue software. The other is the open-source, NDA-free PDK (process design kit) used in designing LSIs. The process of developing and constructing Large Scale Integrated (LSI) circuits within this framework is conducted and assessed. From these trials, the effect of enhancing educational effectiveness on LSI design is indicated. These trials enhanced the contributors’ interest and motivation to understand the details of computer systems and their relation to LSIs. It is also indicated that this framework is effective in enhancing rapid IP development as well as its importance as an educational aspect of open-source software.