Moore's Law Research Articles

Ultra‐Steep‐Slope and High‐Stability of CuInP2S6/WS2 Ferroelectric Negative Capacitor Transistors by Passivation Effect and Dual‐Gate Modulation

AbstractFerroelectric negative capacitance transistors (Fe‐NCFETs) have emerged as a promising technology for low‐power electronics and have the potential to continue Moore's law. However, the existing 2D ferroelectric materials are predominantly sulfides or halides, which are susceptible to oxidation or hydrolysis, thereby hindering their commercial production due to concerns related to performance and stability. To address these obstacles, the authors have optimized the Fe‐NCFETs composed of 2D ferroelectric CuInP2S6 and semiconductor WS2 using high‐k Al2O3 passivation and dual‐gate modulation strategy. With atomic layer deposition (ALD) of Al2O3, all‐2D Fe‐NCFETs, operated at a low driven voltage of 0.3 V, achieve much improvement in stability and performance with a high ON/OFF ratio of 109 and minimum subthreshold swing (SS) of 14 mV dec−1, which is attributed to the negative capacitance effect of CuInP2S6 and passivation effect of ALD‐Al2O3. The dual‐gate modulation approach is also implemented to maintain the device stability and enable the improved ON/OFF ratio from 105 to 108, minimum SS of 10 mV dec−1, and an average SS of ≈60 mV dec−1 covering more than five orders of magnitude of current. This work provides a facile and effective strategy for designing all‐2D Fe‐NCFETs with ultra‐steep SS and high stability, showing exciting potential for future low‐power electronic applications.

(Gordon E. Moore Medal for Outstanding Achievement in SSS&T) Moore’s Law Sustained by Non-Lithographic Technologies

Since G. Moore’s historical observation [1] that the functionality per chip (bits, transistors) as well as MPU performance (clock frequency in MHz × instructions per clock = millions of instructions per second) doubles every 1.5 to 2 years, the semiconductor industry has continued to grow to over 600 G$ in 2022 [2].The IRDS 2022 Roadmap [3] catches the scaling challenges faced for the upcoming decades by the term ‘3D Power Scaling’. This period is the third in a sequence of eras that started early on with straightforward geometrical scaling by continuous shortening of the wavelengths (from regular UV to deep UV/immersion) used in the lithographic patterning of planar transistor structures (Fig. 1a). In the second, almost past ‘equivalent scaling’ era, new superior material properties and critical dimensions nearing single-digit nanometer values could still be realized by cost-effective technology solutions, often in spite of the delay in (EUV) lithography solutions. Ever more complex device architectures requiring extreme edge placement accuracy, layer conformality and shape fidelity in all processing steps (deposition, etching) could be fully 3D-integrated into vertical intra- and inter-chip concepts (Fig. 1b) thus alleviating the need for new capital-intensive lithography tools capable of higher resolution (~ 40% of total tool costs).Figure 2 illustrates the development in the past 65 years of the non-lithographic technologies that have sustained Moore’s Law, as driven by continuous downscaling of CMOS devices. Two extra trends have set in half way (~1993): single-wafer processing and heterogeneous device integration. The latter development, often coined as More than Moore, a term that was introduced in the 2005 ITRS Roadmap, and refers to the silicon-compatible integration of devices with functionalities that do not necessarily scale according to Moore's Law, but provide additional value in different ways. The More-than-Moore approach allows for the incorporation of non-digital functionalities (e.g., RF communication, passive components, power control, sensors, actuators) that can flexibly move from the system board-level into the package (SiP) or onto the chip (SoC).We will discuss a kaleidoscopic view of the author’s activities in Rapid Thermal Processing, RIE etching for TSVs, RF-SIP integration of passives, and Atomic Layer Processing (deposition, etch, and cleaning). In sub-10 nm scaling and fabrication of 3D architectures, especially the techniques of ALD and ALE have manifested to cost-effectively bridge the record incubation time needed to bring EUV technology from prototype to commercial use. More importantly, these unique techniques can be used to create advanced devices in dedicated isotropic (thermal and radical-enhanced) and anisotropic (directional and ion-enhanced) processing modes. Here, energetic species (radicals and/or ions in a plasma) are used in one or two steps, with the ions yielding anisotropic profiles (used in FinFET logic and 3D NAND memory), and neutrals and radicals yielding isotropic profiles used to deposit or etch the features in horizontal nanowires, nanosheets and ‘forksheets’ in GAA-FETs.1. G. Moore, Cramming more components onto integrated circuits, Electronics 38(8), (1965) 114-118.2. https://www.semiconductors.org/global-semiconductor-sales-increase-24-year-to-year-in-october-annual-sales-projected-to-increase-26-in-2021-exceed-600-billion-in-2022/3. International Roadmap for Devices and Systems (IRDS™) 2022 Edition - IEEE IRDS™. Fig. 1. a) Different scaling ages for device manufacturing; b) the planar-to-GAA transition; after [3]. Fig. 2. Historic and future perspectives of non-lithographic key technologies in IC scaling. Figure 1

Binary Addressable Optical Multiplexing Waveguides via Electrochromic Switching

Photonic circuits attract much attention as promising candidates to overcome the drawbacks of their electronic counterparts. By utilizing the broad bandwidth and low energy consumption of optical communication, hybrid circuits can provide a comprehensive platform for the era beyond Moore's law. In particular, parallel matrix operations, the heavy lifting behind neural networks, remain challenging for traditional electronics due to high heat dissipation. To enable these parallel computations optically, (de‐)multiplexing is crucial to address the different channels. Previously this has been accomplished with complex spectral or time encodings in wave division or time division methods. However, herein, a simple method to address parallel optical channels exclusively with 2‐bit signals is presented. By using PEDOT:PSS as electrochromic material for intensity modulation, light transmission or absorption is controlled by oxidation and reduction with an electrolyte. Y‐branch structures are used to design the multiplexing layout and to assign the 2‐bit states to the channels. This binary addressable optical multiplexer, therefore, combines optical communication with electronic signals into a hybrid circuit.

Effect of Different pH in HKMG on the Selection Ratio of Al and Poly Removal Rates

When the characteristic size of integrated circuits developed to 28 nm and below according to Moore’s Law, aluminum was widely used as a gate material in HKMG structures, and the CMP technology of aluminum gates was a breakthrough in the upgrading of HKMG post-gate process technology. Aluminum gate CMP requirements are much higher than aluminum wiring and Damascus wiring, the key to aluminum gate CMP is to achieve high material removal selectivity and high perfect surface. At home and abroad, the research on aluminum gate CMP is mostly concentrated on removal rate and Al–Co galvanic corrosion. This paper will explore the influence of the rate selection ratio of aluminum and polysilicon under glycine hydrogen peroxide system with different pH conditions via CMP experiments, electrochemical experiments, UV and XPS spectroscopy experiments, etc.

Superconducting-Oscillatory Neural Network With Pixel Error Detection for Image Recognition

Brain-inspired oscillatory neural networks (ONNs) utilize coupled oscillators to emulate biological neuronal dynamics. ONNs are naturally suitable for image/pattern recognition. Many hardware implementations of ONNs have been explored recently by using analog or digital CMOS systems, which can be limited by Moore's law. In this work, we used one of the advanced superconducting technologies for coupled oscillator networks to further improve the energy efficiency and processing speed. Inductively coupled ring oscillators using rapid single flux quantum (RSFQ) technology were designed and simulated. These Josephson junction (JJ) based oscillators can operate as fast as tens of GHz but only consume a energy of several aJ per operation. Excluding cryo-cooling factors, the estimated power consumption of our RSFQ oscillator is hundreds of nW at a frequency of 12.5 GHz, which is multiple times smaller than a typical CMOS ring oscillator. Furthermore, a system for pattern recognition with error detection was designed based on these oscillators. Synchronization dynamics in a pair of coupled oscillators were used to identify whether a test pixel matches a reference pixel. A network comprised of 16 pairs of oscillators were wired together, along with synchronization detectors and a fluxon integrator to demonstrate pattern recognition function. This work was performed using standard JJ models and demonstrated through WRspice and JoSIM software simulations. The circuits and systems proposed in this work aim to provide insights into the use of superconducting technology for implementing ONNs and may serve as basic building blocks for the design of more complex oscillatory computational networks in image processing and beyond. Single oscillator modeling and systematic network function exploration will be performed in future work.

Photoemission spectroscopy on photoresist materials: A protocol for analysis of radiation sensitive materials

The continued downscaling, following the so-called Moore's law, has motivated the development and use of extreme ultraviolet (EUV) lithography scanners with specialized photoresists. Since the quality and precision of the transferred circuit pattern are determined by the EUV-induced chemical changes in the photoresist, having a deep understanding of these chemical changes is of pivotal importance. For this purpose, several spectroscopic and material characterization techniques have already been employed. Among them, photoemission can be essential as it not only allows direct probing of chemical bonds in a quantitative way but also provides useful information regarding the generation and distribution of primary and secondary electrons. However, since high energy photons are being employed for characterization of a photosensitive material, modification of the sample during the measurement is possible, and this must be considered when investigating the chemical changes in the photoresist before and after exposure to EUV light. In this paper, we investigate the chemical changes occurring during the photoemission measurements of an unexposed, model chemically amplified resist based on the well-known environmentally stable chemically amplified photoresist as a function of a number of measurement parameters, using both an x ray (AlKα, 1486.6 eV) and a UV source (HeII, 40.8 eV). We will show that these chemical changes can be simulated through theoretical modeling of the photoemission spectra. Based on these results, we propose a measurement protocol allowing to minimize or eliminate this modification which will help to guide (or enable) photoemission measurements on radiation-sensitive materials (e.g., photoresists).

A review on source and drain formation in FinFETs

Silicon chip technology has been developing in accordance with Moores Law since its inception. As the device size shrinks, the transistor channel also shrinks. But when the channel is reduced to a point where electrons are free to travel between the source and drain, the transistor loses its switching power and the logic circuit becomes useless. Therefore, 3D fin field effective transistors (FinFETs) was designed to address the issue. This article highlights that compared to 2D MOSFETs, how difficult the process of source and drain formation in 3D FinFETs. The discussion focuses on the ion implantation and annealing technologies within the fabrication process.

Design and fabrication of nanometer measurement platform for better understanding of silicon mechanical properties

Semiconductor industry is experiencing unprecedented growth, still driven by Moore's law, which is continually delivering devices with improved performance at lower costs. The continuation of this development places the industry in a divergent trade-off between economic attractiveness, technological feasibility, and the need for further performance improvement. Since the mainstream semiconductor technologies are silicon-based, new disruptive innovations are needed to gain additional performance margins. The use of nanowires is the preferred approach for preserving electrostatic control in the MOS transistor channel, and the application of mechanical stress is a booster of carrier mobility. It is in this context that this paper presents the design, fabrication, theoretical modeling, and characterization of a measurement platform to characterize the mechanical tensile stress of extremely narrow Si nanowires as small as 14.2 ± 1.12 nm in width. The proposed measurement platform enables a precise control of uniaxial strain, in terms of both amplitude and location, through the implementation of a stoichiometric Si3N4 pulling strand exerting a high tensile force on silicon nanowires. Reported devices are fabricated using a silicon-on-insulator wafer with fully complementary metal–oxide–semiconductor-compatible processing and top-down approach. It is observed that the mechanical strength of nanostructured Si is size-dependent and increases with miniaturization. Characterization revealed a record tensile strength value of 7.53 ± 0.8% (12.73 ± 1.35 GPa) for the narrowest nanowires fabricated using a top-down approach.

U.S. shale oil production and trend estimation: Forecasting a Hubbert model

AbstractScarcity and growth analyses about energy include forecasting extraction rates of non‐renewable resources while taking into account technological progression. One mechanism, Moore's (1965) Law of technological improvement, encompasses experience enhanced steady cost reductions. Alternatively, synthesis technological change refers to unforeseen innovative breakthroughs. These trends relate to the Hubbert (1956, 1962) Curve of U.S shale oil extraction in the U.S. Lower 48 contiguous states. Price effects, drilling rigs and the price‐to‐drilling rig relationship are analyzed. Results show we are at peak U.S. shale oil, and could experience comprehensive decline. This implies Catton's (1982) “Age of Exuberance,” and “Carrying Capacity” drawdown.

Progress in the Synthesis and Application of Tellurium Nanomaterials.

In recent decades, low-dimensional nanodevices have shown great potential to extend Moore's Law. The n-type semiconductors already have several candidate materials for semiconductors with high carrier transport and device performance, but the development of their p-type counterparts remains a challenge. As a p-type narrow bandgap semiconductor, tellurium nanostructure has outstanding electrical properties, controllable bandgap, and good environmental stability. With the addition of methods for synthesizing various emerging tellurium nanostructures with controllable size, shape, and structure, tellurium nanomaterials show great application prospects in next-generation electronics and optoelectronic devices. For tellurium-based nanomaterials, scanning electron microscopy and transmission electron microscopy are the main characterization methods for their morphology. In this paper, the controllable synthesis methods of different tellurium nanostructures are reviewed, and the latest progress in the application of tellurium nanostructures is summarized. The applications of tellurium nanostructures in electronics and optoelectronics, including field-effect transistors, photodetectors, and sensors, are highlighted. Finally, the future challenges, opportunities, and development directions of tellurium nanomaterials are prospected.

An optical digital‐to‐analog converter with a built‐in intensity converter consisting of silicon waveguide

AbstractOptical digital‐to‐analog converters (DACs) are key to overcoming the enormous power consumption caused by the slowdown of Moore's Law. In previous work, an optical DAC consisting of a signal generator and an intensity converter was presented. The generating component was integrated into the device, but a higher level of device integration is desirable. An optical DAC device with a built‐in intensity converter for a 2‐bit binary phase‐shift keying (BPSK) signal is demonstrated. The integrated device consists of two delay line interferometers (DLIs) with silicon waveguides. The first is used to generate a quadrature PSK (QPSK) signal from two BPSK signals, and the second is used to convert the QPSK constellation into light intensities. Experimental results show that the 2‐bit digital codes 00, 01, 10, and 11 can be successfully converted into four different light intensities depending on their pattern at 10 Gbps.

2D Short‐Channel Tunneling Transistor Relying on Dual‐Gate Modulation for Integrated Circuits Application

AbstractWith continuous size scaling, the surface dangling bonds and short‐channel effects will degrade silicon based transistor performance. Thus, it is of great importance to seek new channel materials and transistor architectures to further continue Moore's law. Herein, a new ultra‐thin short‐channel tunneling transistor is developed comprising all 2D‐ components. Distinct from usual 2D planar transistor, this device is configured with vertical MoS2/WSe2 junction and in‐plane WSe2 channel, the switch states are realized by the gate‐regulated barrier height of heterojunction, enabling the transition of transport mechanism between thermionic‐emission and tunneling. Under dual‐gate configuration, the transistor exhibits high performance with drive current of 4.58 µA, on/off ratio of 4 × 107, subthreshold swing (SS) of 97 mV decade−1 and drain‐induced barrier lowering (DIBL) of 12 mV V−1, that can meet the requirement of logical applications in integrated circuits (IC). Taking advantage of the high‐speed tunneling current and unique short‐channel architecture, the device overcomes the issues of voltage spikes and long reverse recovery time that exist in usual electric components, and thus gains an access to the IC interface. This work provides a proof‐of‐concept transistor architecture relying on dual‐gate modulation, opening up a promising perspective for next generation low‐power, high‐density, and large‐scale IC technologies.

Multimode Optical Interconnects on Silicon Interposer Enable Confidential Hardware-to-Hardware Communication.

Following Moore's law, the density of integrated circuits is increasing in all dimensions, for instance, in 3D stacked chip networks. Amongst other electro-optic solutions, multimode optical interconnects on a silicon interposer promise to enable high throughput for modern hardware platforms in a restricted space. Such integrated architectures require confidential communication between multiple chips as a key factor for high-performance infrastructures in the 5G era and beyond. Physical layer security is an approach providing information theoretic security among network participants, exploiting the uniqueness of the data channel. We experimentally project orthogonal and non-orthogonal symbols through 380 μm long multimode on-chip interconnects by wavefront shaping. These interconnects are investigated for their uniqueness by repeating these experiments across multiple channels and samples. We show that the detected speckle patterns resulting from modal crosstalk can be recognized by training a deep neural network, which is used to transform these patterns into a corresponding readable output. The results showcase the feasibility of applying physical layer security to multimode interconnects on silicon interposers for confidential optical 3D chip networks.

ПРО КОНЦЕПЦІЮ ОРГАНІЗАЦІЇ БОРОТЬБИ З БЕЗПІЛОТНИМИ ЛІТАЛЬНИМИ АПАРАТАМИ В МІСЦЯХ ЗБЕРІГАННЯ ЗАСОБІВ УРАЖЕННЯ

The history of small-sized, low-speed unmanned aerial vehicles, in contrast to the history of unmanned aerial vehicles, is not counted for half a century, but only for two dozen years. The first publications devoted to small-sized and low-speed unmanned aerial vehicles were published after 2008. The number of publications on the specified subject significantly increased in 2017-2018. It is during this period that military operations using small-sized and low-speed unmanned aerial vehicles become widespread. As an example, we can mention the attacks on the oil refinery in Saudi Arabia in September 2019, the attack on the airport in the city of Jizan in the same Saudi Arabia in July 2020, the attacks on the Russian air base in the Syrian city of Khmeimi in 2019-2020. Almost every day, from the regions of the planet where armed conflict is taking place, there are reports of the destruction of storage places of weapons and means of destruction, which affects the course of armed conflicts. It is significant that unmanned aircraft are increasingly being used to destroy weapons. The article highlights the factors that determine the effectiveness of the use of unmanned aerial systems for the destruction of weapons storage sites, and predicted dynamic changes in these factors. The rapid development of microelectronic technologies, which is currently observed, became the basis for the improvement of unmanned aircraft systems, the expansion of the range of tasks performed by unmanned aircraft, the emergence of new classes of devices and the improvement of the tactics of their use. The rapid development of microelectronics is also considered from the point of view of confirming Moore's law, forecasts for the near future, clarifications of the law for the present time, clarifications of forecasts for the next 15 years. Conceptually, the opinions of the authors regarding the minimization of losses of weapons of destruction are presented, the basis of which are their own observations of the statistics of losses from storage sites of weapons of destruction of the Armed Forces of Ukraine for the period from 2003 to 2018, the causes of losses. Keywords: means of defeat, unmanned aerial vehicle, storage places, logistic security.

Triboelectric-potential configurable MoTe2 homojunction for photovoltaic device and logic circuits

Reconfigurable devices based on two-dimensional materials are considered as one of the ways to extend Moore's Law. However, most reconfigurable devices use a gate voltage to dope the channel electrostatically, and the continuously applied gate voltage poses the problem of high device power consumption. Here, for the first time, we propose a tribotronic reconfigurable MoTe2 field effect transistor, where the power consumption of the device is greatly reduced by using triboelectric potentials generated by external mechanical operations instead of applying gate voltages. The drain current noise spectral density test proves that no additional current noise interferes with the output current during mechanical operation. Mechanical operation allows facile modulation of four different channel polarities (n-n, p-p, p-n, and n-p) in a single transistor. We demonstrate the potential application of a tribotronic p-n diode for photovoltaic device. The logic circuit composed of two tribotronic reconfigurable transistors realizes the logic functions of inverter, AND gate, and OR gate. Our device extends tribotronic logic and demonstrates great potential for human-machine interaction, intelligent sensors, and wearable devices.

Single-Charge Tunneling in Codoped Silicon Nanodevices.

Silicon (Si) nano-electronics is advancing towards the end of the Moore's Law, as gate lengths of just a few nanometers have been already reported in state-of-the-art transistors. In the nanostructures that act as channels in transistors or depletion layers in pn diodes, the role of dopants becomes critical, since the transport properties depend on a small number of dopants and/or on their random distribution. Here, we present the possibility of single-charge tunneling in codoped Si nanodevices formed in silicon-on-insulator films, in which both phosphorus (P) donors and boron (B) acceptors are introduced intentionally. For highly doped pn diodes, we report band-to-band tunneling (BTBT) via energy states in the depletion layer. These energy states can be ascribed to quantum dots (QDs) formed by the random distribution of donors and acceptors in such a depletion layer. For nanoscale silicon-on-insulator field-effect transistors (SOI-FETs) doped heavily with P-donors and also counter-doped with B-acceptors, we report current peaks and Coulomb diamonds. These features are ascribed to single-electron tunneling (SET) via QDs in the codoped nanoscale channels. These reports provide new insights for utilizing codoped silicon nanostructures for fundamental applications, in which the interplay between donors and acceptors can enhance the functionalities of the devices.

Progress in Bioinspired Photodetectors Design for Visual Information Processing

AbstractRapid development of modern science and technology has prompted explosive growth of data volumes, especially the visual information, which brings heavy pressure on information processing and computation. The classic technical route to improve the computation power of image processing units by reducing the critical dimension of the transistors according to Moore's law gradually fails due to the physical limit of transistors’ footprint and the separated architectures. Inspired by human vision systems, retina‐like photodetectors that mimic their spatial and temporal properties have attracted widespread attention. These developed architectures enable the early data processing in‐ or near‐sensor, significantly reducing the computing power required in the back end. Herein, a comprehensive review on bioinspired photodetectors that possess the spatial and temporal properties of biological vision is provided. The properties of retina are summarized and presented first. Basic structure design and operation mechanism of those photodetectors with spatial properties of retina (including the distribution of receptive fields and the shape of the hemisphere) and temporal properties of retina (including the memory properties enabled learning and the light intensity adaptation) are reviewed thoroughly. Eventually, challenges and future perspectives are commented and provided to facilitate the rapid development of in‐ or near‐sensor computing photodetectors.

Introduction to machine leaning in electronic design automation (EDA)

The rapid growth of the intergraded circuit industry as predicted by Moores law has significantly increased the importance of efficient design processes. In addition, due to physical constraint, we will soon reach the limit of how small the size of the transistor can become, and the design processes will become more complex than ever. In order to cope with those challenges and introduce the product to the market within the time to market, the industry has been developing ways to apply machine learning to concurrent EDA tools. This paper will aim to introduce how machine learning is applied to varies processes of electronic design and how they improve the current EDA tools. We will also show the limitations and opportunities of ML based EDA tools and provide a rough idea of the potential future to those who are looking into this area.

Where digital meets physical innovation: Reverse salients and the unrealized dreams of3Dprinting

AbstractFor more than three decades, enthusiasts have predicted that direct manufacturing enabled by 3D printing would inevitably supplant traditional manufacturing methods. Alas, for nearly as long, these utopian predictions have failed to materialize. One reason is a flawed assumption that hybrid digital‐physical systems such as 3D printing would advance as rapidly as purely digital innovations enabled by Moore's law. Instead, like other examples of cyber‐physical systems (CPSs), technological progress in 3D printing faces inherent limitations that are emblematic of the differences between CPSs and purely digital innovations. As with any complex CPS, improved performance of a 3D printing system has been limited by that of its key components—the sort of limiting problem previously defined as a reverse salient. Unlike previously studied technologies, several reverse salients for 3D printing performance have neither resolved nor signs of resolving soon. Here we analyze these key reverse salients, and show how they have hampered the suitability of 3D printing for direct manufacturing and other predicted applications. We contrast predicted versus actual capabilities for 3D printing‐enabled transformation in six key areas: product innovation, mass customization, home fabrication, distributed manufacturing, supply chain optimization and business model innovation. From this, we suggest opportunities for greater realism in future 3D printing research, as well as broader implications for our understanding of CPSs and reverse salients.

Imaging mechanism and contrast separation in low-voltage scanning electron microscopy imaging of carbon nanotube arrays on SiO2/Si substrate

Polymer-sorted high-density carbon nanotube (CNT) arrays have shown great potential to extend the silicon-based Moore's law. Imaging the CNT arrays on insulators like SiO2/Si using low-voltage scanning electron microscopy (LVSEM) to acquire array information like the alignment, density, and distribution of residual polymers is necessary. Such a task remains challenging due to the nanoscale CNT body (1–2 nm in diameter), nanoscale tube-to-tube separation (1–10 nm), the broadening of the apparent diameter, and the complex image contrast caused by the insulating substrate and polymer residues. In this study, the imaging mechanism for this system is investigated. Two methods are developed to separate the three dominant contrasts, i.e. topographic contrast, charge contrast, and material contrast, by selecting the take-off angle and energy of the emitted electrons as enabled by changing the working distance or the deceleration voltage. The contrast formation and separation mechanism is further confirmed by the dynamic contrast evolution due to the electron-beam-induced deposition of amorphous carbon. The contrast separation method is further applied to an individual CNT, reducing its apparent diameter from 36 nm to 6 nm. This result hints at the potential for LVSEM to count the density exceeding 150 CNTs/μm of CNT arrays. Finally, a comparative study of LVSEM and transmission electron microscopy confirms the failure of LVSEM to resolve CNTs in a bundle. The results suggest that the density of CNT arrays may be underestimated in reported SEM data. The proposed method can serve as a useful tool for further study and application of arrayed CNTs.