A review on source and drain formation in FinFETs

Abstract

Silicon chip technology has been developing in accordance with Moores Law since its inception. As the device size shrinks, the transistor channel also shrinks. But when the channel is reduced to a point where electrons are free to travel between the source and drain, the transistor loses its switching power and the logic circuit becomes useless. Therefore, 3D fin field effective transistors (FinFETs) was designed to address the issue. This article highlights that compared to 2D MOSFETs, how difficult the process of source and drain formation in 3D FinFETs. The discussion focuses on the ion implantation and annealing technologies within the fabrication process.