3D FinFET for Next Generation Nano Devices

Abstract

Miniaturization has been a constant challenge to meet the demands of high performance, high density, low power and low voltage complex devices. Miniaturization is the main driving force for the migration from micro electronic device structures to Nano electronic device structures. Planar CMOS scaling has been delivering better performance & low power devices at each cutting edge of the technology node for more than three decades. Now, CMOS scaling is facing crucial limitations and some show stoppers are affecting bulk CMOS scaling. So, semiconductor industry is witnessing the phase-out of Planar CMOS with the introduction of new device architecture like 3D FinFET technology for extending the Moore's Law for Nanoscale technologies. This paper discusses the evolution of Planar CMOS technology, CMOS scaling challenges, Planar CMOS optimization technologies & the next generation Nano architectures in order to extend the scaling beyond planar CMOS. FinFET is emerging technology beyond 22nm. This paper studies FinFET architecture, advantages and manufacturing challenges associated with it. It also throws light on future technologies like Carbon nanotube, Silicon Nanowire FET and Tunneling FET etc.