Monolithic Integration Technology Research Articles

Room-temperature 2D semiconductor activated vertical-cavity surface-emitting lasers

Two-dimensional (2D) semiconductors are opening a new platform for revitalizing widely spread optoelectronic applications. The realisation of room-temperature vertical 2D lasing from monolayer semiconductors is fundamentally interesting and highly desired for appealing on-chip laser applications such as optical interconnects and supercomputing. Here, we present room-temperature low-threshold lasing from 2D semiconductor activated vertical-cavity surface-emitting lasers (VCSELs) under continuous-wave pumping. 2D lasing is achieved from a 2D semiconductor. Structurally, dielectric oxides were used to construct the half-wavelength-thick cavity and distributed Bragg reflectors, in favour of single-mode operation and ultralow optical loss; in the cavity centre, the direct-bandgap monolayer WS2 was embedded as the gain medium, compatible with the planar VCSEL configuration and the monolithic integration technology. This work demonstrates 2D semiconductor activated VCSELs with desirable emission characteristics, which represents a major step towards practical optoelectronic applications of 2D semiconductor lasers.

Towards Large-Scale Fast Reprogrammable SOA-Based Photonic Integrated Switch Circuits

Due to the exponentially increasing connectivity and bandwidth demand from the Internet, the most advanced examples of medium-scale fast reconfigurable photonic integrated switch circuits are offered by research carried out for data- and computer-communication applications, where network flexibility at a high speed and high connectivity are provided to suit network demand. Recently we have prototyped optical switching circuits using monolithic integration technology with up to several hundreds of integrated optical components per chip for high connectivity. In this paper, the current status of fast reconfigurable medium-scale indium phosphide (InP) integrated photonic switch matrices based on the use of semiconductor optical amplifier (SOA) gates is reviewed, focusing on broadband and cross-connecting monolithic implementations, granting a connectivity of up to sixteen input ports, sixteen output ports, and sixty-four channels, respectively. The opportunities for increasing connectivity, enabling nanosecond order reconfigurability, and introducing distributed optical power monitoring at the physical layer are highlighted. Complementary architecture based on resonant switching elements on the same material platform are also discussed for power efficient switching. Performance projections related to the physical layer are presented and strategies for improvements are discussed in view of opening a route towards large-scale power efficient fast reprogrammable photonic integrated switching circuits.

A Novel Si–GaN Monolithic Integration Technology for a High-Voltage Cascoded Diode

In this letter, a novel approach for monolithic integration of Si-based and GaN-based devices on Si substrate for high-voltage power switching applications is reported. To enable the integration, AlGaN/GaN epitaxial growth is carried out in recessed windows on a Si (111) substrate by selective epitaxial growth. A cascoded diode formed by series connection of a Si diode and a normally- ON AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistor is experimentally demonstrated by using this technology. The cascoded diode features a breakdown voltage of 557 V and a differential specific ON-resistance of 2.8 $\text{m}\Omega \cdot $ cm2 at 500 A/cm2. Its reverse leakage current is two orders of magnitude lower compared with the conventional AlGaN/GaN Schottky barrier diode. The characterization results of the fabricated cascoded diode demonstrate that the proposed Si–GaN monolithic integration technology is compatible with both Si and GaN fabrication processes.

Cell-on-Buffer: New design approach for high-performance and low-power monolithic 3D integrated circuits

Monolithic 3D Integration technology (M3D) provides high density vertical interconnects allowing new design approaches such as Cell-on-Cell (gate level approach) and NMOS-on-PMOS (transistor level approach). This work proposes a 3D Cell-on-Buffer (3DCoB) design approach by separating the logical functioning stage of a gate from its driving stage, then vertically stacking them. The proposed 3DCoB approach demonstrates better performances compared to the 2D implementation and the conventional 3D approaches. A Multi-VDD low-power technique is applied to 3DCoB cells (i.e. a different power supply for each tier). The multi-VDD 3DCoB technique provides total power reduction with limited performances degradation compared to the single-VDD 3DCoB approach. 3DCoB with single- and Multi- VDD techniques are applied on a set of benchmark designs in 28nm-FDSOI technology using conventional sign-off place and route flow. Implementation results show up to 35% increment in performance and up to 21.8% reduction in the total power compared to 2D designs.

InP-Based Monolithic Integration Technologies for 100/200Gb/s Pluggable Coherent Transceivers

InP-Based Monolithic Integration Technologies for 100/200Gb/s Pluggable Coherent Transceivers

Near-infrared electroluminescence and photo detection in InGaAs p-i-n microdisks grown by selective area growth on silicon

Microselective-area growth of p-i-n InGaAs disks on (111) silicon by metalorganic chemical vapor deposition is a promising technology for III/V-on-Si integration. As a proof-of-concept, room-temperature electroluminescence is reported from ensembles of p-i-n InGaAs-on-Si micro-disks. The observed spectrum shows peak luminescence at 1.78 μm with a local maxima at 1.65 μm. The disks are also shown to generate a measurable photo current when illuminated by infrared light with less energy than the silicon bandgap energy. This makes these InGaAs-on-Si disks a promising technology for monolithic integration of light sources and detectors with silicon photonics and complementary metal-oxide-semiconductor electronics for optical communication, sensing, and imaging.

MEMS Monolithic Integration Technology

The monolithic integrated technology of MEMS was discussed. First discussed the advantages and difficulties faced by the MEMS monolithic integration technology. Second the features and the process of the mainstream MEMS monolithic integration technology was introduced. And finally put forward a SOI MEMS monolithic integration technology, the technology with no high-temperature process, Post-CMOS integrated solution, compatible with the CMOS process. This technology can achieve high aspect ratio, high-performance micro-inertial devices..

Monolithic AWG-based Discretely Tunable Laser Diode With Nanosecond Switching Speed

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A novel concept for an arrayed-waveguide-grating (AWG)-based fast tunable laser is presented. It is fabricated in the InP–InGaAsP monolithic integration technology. Laser peaks have a sidemode suppression ratio of 30–40 dB. The wavelength switching speed is in the order of a few nanoseconds and switching is achieved by a 1-mA bias current. The switching between AWG channels is discrete and no laser operation takes place at wavelengths corresponding to other channels during the tuning process. </para>

AMiBA: BROADBAND HETERODYNE COSMIC MICROWAVE BACKGROUND INTERFEROMETRY

The Y. T. Lee Array for Microwave Background (AMiBA) has reported the first results on the detection of galaxy clusters via the Sunyaev–Zel'dovich effect. The objectives required small reflectors in order to sample large-scale structures (20'), while interferometry provided modest resolutions (2'). With these constraints, we designed for the best sensitivity by utilizing the maximum possible continuum bandwidth matched to the atmospheric window at 86–102 GHz, with dual polarizations. A novel wide-band analog correlator was designed that is easily expandable for more interferometer elements. Monolithic millimeter-wave integrated circuit technology was used throughout as much as possible in order to miniaturize the components and to enhance mass production. These designs will find application in other upcoming astronomy projects. AMiBA is now in operation since 2006, and we are in the process to expand the array from seven to 13 elements.

Demonstration and Characterization of Bipolar Monolithic Integrated Circuits in 4H-SiC

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A monolithic bipolar integrated circuit technology employing transistor–transistor logic (TTL) is demonstrated in 4H-SiC for the first time. Operating on a 15-V power supply, as required by the higher base–emitter voltage of SiC bipolar transistors, TTL inverters with a fan-out of ten exhibit high-level noise margin <formula formulatype="inline"><tex>$(\hbox{NM}_{H})$</tex></formula> of 1.5 V and low-level noise margin <formula formulatype="inline"><tex>$(\hbox{NM}_{L})$</tex></formula> of 3.9 V at room temperature. The transient response of the fabricated SiC TTL gates is also characterized. The circuits operate satisfactorily from room temperature to above 300 <formula formulatype="inline"><tex>$^{\circ}\hbox{C}$</tex></formula>, suggesting that SiC bipolar integrated circuits are promising candidates for high-temperature applications. </para>

Structure and Magnetism of Ba-Hexaferrite Films Grown on Single Crystal 6-H SiC With Graduated Interfacial MgO Buffer Layers

M-type barium hexaferrite films were processed by pulsed laser deposition on single-crystal 6-H silicon carbide substrates. MgO buffer and barrier layers were introduced to improve the film quality. Samples were characterized by X-ray photoelectron spectroscopy, atomic force microscopy, scanning electron microscopy, X-ray diffraction, vibrating sample magnetometry, and ferromagnetic resonance (FMR). X-ray thetas-2thetas diffraction measurements indicated a strong (0, 0, 2n) crystallographic alignment. The magnetization of the BaM film is comparable to bulk values (4piM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> ~4320 G). A derivative power FMR linewidth of 500 Oe was measured at 55 GHz for the as-deposited films. This paper explores a potential next generation of microwave and millimeter-wave monolithic integrated circuit technology based upon a wide band-gap semiconducting material

Polylithic integration of electrical and optical interconnect technologies for gigascale fiber-to-the-chip communication

Polylithic integration of electrical and optical interconnect technologies is presented as a solution for merging silicon CMOS and compound semiconductor optoelectronics. In contrast to monolithic and hybrid integration technologies, polylithic integration allows for the elimination of optoelectronic and integrated optic device-related processing from silicon CMOS manufacturing. Printed wiring board-level and compound semiconductor chip-level waveguides terminated with volume grating couplers facilitate bidirectional optical communication, where fiber-to-board and board-to-chip optical coupling occurs through a two-grating (or grating-to-grating) coupling path. A 27% increase in the electrical signal I/O projected by and 33% increase in the number of substrate-level electrical signal interconnect layers implied by the International Technology Roadmap for Semiconductors (ITRS) projections for the 32-nm technology generation are required to facilitate 10 Tb/s aggregate bidirectional fiber-to-the-chip communication. Buried air-gap channels provide for the routing of chip or board-level encapsulated air-clad waveguides for minimum crosstalk and maximum interconnect density. Optical signals routed on-board communicate with on-chip volume grating couplers embedded as part of a wafer-level batch package technology exhibiting compatible electrical and optical input/output interconnects. Measurements of grating-to-grating coupling reveal 31% coupling efficiency between two slab, nonoptimized, nonfocusing volume grating couplers.

Design and Fabrication of Silcon Microlens with Low SAG for 528(H) � 528(V) Infrared Charge-Coupled Device Application

Microlens array is an important optical element to improve the photosensitivity of charge-coupled device (CCD). In this paper, a monolithic integration technology between microlens and 528 × 528 element PtSi Schottky-barrier infrared charge-coupled device (IRCCD) with a pixel size of 30μm × 30μm has been developed. The microlens array with low sag and long focal length is designed based on geometrical optics theory. It is directly formed on the back side of the substrate in IRCCD chip using successive photolithography and A+ ion beam etching (IBE) technology. The microlens array is characterized by both surface stylus and point spread function (PSF). The experiment results of integration device between IRCCD and microlens array indicate that the optical signal response is improved obviously and a responsivity increase by a factor of 1.8 in the operation band.

Monolithic integration technology between microlens arrays and infrared charge coupled devices

In this paper, we develop an integration technology between Si microlens and 256(H)×256(V) element PtSi Schottky-barrier infrared charge coupled device (IR-CCD) to improve the optical responsivity of CCD sensor. The refractive microlenses with the pixel size of approximately 28×28 μm 2 is directly fabricated on the backside of CCD substrate to focus the incident irradiation onto the active area. For the integration device the fill factor is improved by a factor of 2.1. As a result, the IR-CCD image sensors operating at 77 K indicate an approximate 0.06–0.4 increase in relative optical responsivity in the spectral range of from 1 to 5 μm . CCD imaging quality with microlens has been improved comparing to that without microlens to a great extent.

Tuning of elliptic whispering-gallery-mode microdisk waveguide filters

High-Q semiconductor microdisk resonators laterally coupled to optical waveguides serve as compact and robust components in wavelength-division-multiplexing systems. We present an efficient algorithm for the two-dimensional design of wavelength-selective filters based on waveguide-coupled whispering-gallery-mode (WGM) microresonators of arbitrary cross-sectional shape. A full-wave integral equation formulation enables us to accurately account for the coupling between the resonator and bus waveguide as well as for radiation and material losses. Furthermore, we apply this approach to the analysis of elliptic-resonator filters. Filter tuning by changing the resonator shape from circular to elliptic reduces the dependence of the coupling efficiency on the width of the air gap. Two alternative coupling designs are suggested for monolithic and hybrid integration technologies. One is based on increasing the coupling length, while the other exploits the field concentration at the increased-curvature portion of the deformed WGM resonator.

Leakage Current Behavior in Common I-Layer A-SI:H P-I-N Photodiode Arrays

AbstractHydrogenated amorphous silicon photodiode arrays form the basis of monolithic three-dimensional integrated circuit sensor technology. In these arrays, the intrinsic a-Si:H layer covers the entire area to maximize light collection. One technique by which the pixel diode is defined, is to pattern the bottom contact layer independently of the intrinsic layer. One of the most important characteristics of any diode array, however, is that the dark-state reverse bias leakage currents must be as low as possible to minimize diode noise. This study examines the leakage currents associated with the pixelated array. These structures are unique in that the edge of the diode is defined by the local electric field between diodes, rather than the physical surface of an a-Si:H film. The effect of the diode edge has been found to induce a field-dependent component to the reverse bias leakage current. For example, diodes with 5500Å i-layer, have a junction leakage of 14 to 20 pA/cm2, at 5.0 x 104 V/cm, while the pixel edge-dependent current component can be as high as 30 pA/cm2. In addition, it will be shown that the i-layer thickness and junction doping plays a key role in determining the behavior of the leakage currents.

Technology and First Electrical Characteristics of Complementary NPN and PNP InAlAs/InGaAs Heterojunction Bipolar Transistors

A selective molecular beam epitaxy (MBE) regrowth approach is presented and applied in the demonstration of complementary InP heterojunction bipolar transistor (HBT) technology for monolithic integration of NPN and PNP HBTs. State-of-art performance has been observed: The DC gain was 35 for both integrated NPN and PNP HBTs. fT of 79.6 GHz and fmax of 109 GHz were achieved for NPN devices while fT of 11.6 GHz and fmax of 22.6 GHz were achieved for PNP devices. Little performance degradation has been observed compared with same design NPN or PNP HBT layers grown on individual substrates. Monolithic microwave integrated circuits (MMICs) based on complementary InP HBT technology have been studied for the first time using this technology and their electrical characteristics are presented.

Hybrid Integration of III-V Optoelectronic Devices on Si Platform Using BCB

ABSTRACTIntegration of dense arrays of high frequency III-V photoemitters and photodetectors with Si platform is one of the challenging tasks for realization of novel chip-level optical interconnects. These interconnects require the resolution of numerous problems of compatibility of materials. Comparison of monolithic and hybrid integration technologies highlights the advantages of hybrid approaches for emitters highly sensitive to growth defects. A novel protocol for fabrication of III-V optoelectronic components on a Si platform is proposed. Reversed vertical cavity surface emitting laser (VCSEL) structures were grown homoepitaxialy by MBE on a GaAs substrate, and then bonded to a Si wafer using a benzocyclobutene (BCB) polymer. The GaAs substrate was subsequently removed by selective etching down to an AlAs etch stop layer. This reduces thermal stresses in order to enhance the optoelectronic device performance and increase lifetime. A 10 μm-thick high frequency VCSEL with coplanar metallization is processed on Si with PMGI reflow planarization. Electro-luminescence spectrum, I-V and P-T characteristics were measured and compared with a reference structure. It was found that measured thermal resistance is about five times higher than for devices on a host GaAs wafer.

Two-step metalorganic chemical vapor deposition growth of piezoelectric ZnO thin film on SiO2/Si substrate

Piezoelectric ZnO thin films deposited on semiconductor substrates are used for surface and bulk acoustic wave and devices, which offer advantages such as low power consumption, circuit miniaturization, and cost reduction by integration with microwave monolithic integrated circuit technology. Furthermore, temperature compensated surface acoustic wave (SAW) devices, which are attractive for both communication and sensor technologies, may be achieved in the ZnO/SiO2/Si system as ZnO and Si have positive temperature coefficients of delay, while SiO2 has a negative one. In the present work, ZnO thin films were grown on SiO2/Si substrates by metalorganic chemical vapor deposition. The structural properties of the films were investigated using x-ray diffraction, scanning electron microscopy, and scanning probe microscopy. A two-step growth process was developed to obtain ZnO films with both good crystalline quality and surface morphology. The SAW properties of the ZnO/SiO2/Si system were investigated through modeling and computer simulation based on the transfer matrix method. Acoustic velocity dispersion data obtained from measurement on testing structures agree well with the dispersion curves predicted by computer simulation. The results show that the ZnO/SiO2/Si system is promising for fabricating low-loss SAW devices.

Monolithic Integration of Resonant Tunneling Diodes, Schottky Barrier Diodes and 0.1-µm-gate High Electron Mobility Transistors for High-Speed ICs

Monolithic integration technology for resonant tunneling diodes (RTDs), Schottky barrier diodes (SBDs), and 0.1-µm-gate high electron mobility transistors (HEMTs) was developed. The integration process was investigated to overcome the difficulty in fabricating both RTDs with a mesa height of 530 nm and HEMTs with a gate length of 0.1 µm. The HEMT and SBD structures were grown by metalorganic chemical vapor deposition (MOCVD) on a 2-inch InP substrate. The RTD structure was regrown by molecular beam epitaxy (MBE) on the top layer grown by MOCVD. The characteristics of the fabricated devices showed good uniformity. An analog-to-digital converter and a selector circuit fabricated with these devices operated properly. The presented integration technology is a promising way to provide novel circuits with RTDs, SBDs and 0.1-µm-gate HEMTs.