Monolithic Circuit Research Articles

An ultra-high speed monolithic clock recovery circuit in 0.2-µm GaAs process

This paper presents a 37 Gb/s phase locked-loop (PLL)-type clock recovery (CR) circuit designed and fabricated in 0.2-µm GaAs PHEMT process. The resonator of the modified LC-VCO is based on a compact circuit topology with high Q-value and better isolation. The active amplifier of the VCO is optimized with a combination of several circuit techniques to reduce phase noise and increase the operation speed. Resonant filters containing high-quality CPWs are employed in the signal preprocessor to accommodate the 37 Gb/s data rate. The measured figure of merit of the modified VCO is about ?196 dBc/Hz at 37-GHz when the PLL is locked. The experimental results also demonstrate that the recovered clock signal of the CR circuit has a phase noise of ?81.66 dBc/Hz at 50 kHz off the center frequency.

An improved analytical model of 4H-SiC MESFET incorporating bulk and interface trapping effects

An improved analytical model for the current—voltage (I–V) characteristics of the 4H-SiC metal semiconductor field effect transistor (MESFET) on a high purity semi-insulating (HPSI) substrate with trapping and thermal effects is presented. The 4H-SiC MESFET structure includes a stack of HPSI substrates and a uniformly doped channel layer. The trapping effects include both the effect of multiple deep-level traps in the substrate and surface traps between the gate to source/drain. The self-heating effects are also incorporated to obtain the accurate and realistic nature of the analytical model. The importance of the proposed model is emphasised through the inclusion of the recent and exact nature of the traps in the 4H-SiC HPSI substrate responsible for substrate compensation. The analytical model is used to exhibit DC I–V characteristics of the device with and without trapping and thermal effects. From the results, the current degradation is observed due to the surface and substrate trapping effects and the negative conductance introduced by the self-heating effect at a high drain voltage. The calculated results are compared with reported experimental and two-dimensional simulations (Silvaco®-TCAD). The proposed model also illustrates the effectiveness of the gate—source distance scaling effect compared to the gate—drain scaling effect in optimizing 4H-SiC MESFET performance. Results demonstrate that the proposed I–V model of 4H-SiC MESFET is suitable for realizing SiC based monolithic circuits (MMICs) on HPSI substrates.

Design of Wideband CPW Fed Slotted Microstrip Patch Antenna

Microstrip Patch antennas are very prevalent these days due to various attractive features possessed by them. Coplanar Waveguide (CPW) fed patch antenna has benefits of compact size, ease of fabrication and integration with other monolithic circuits. Moreover, the proposed design is very simple design fed with CPW feed. The proposed antenna performs dual band (1.5 GHz and 7 GHz) operation with later band being wideband ranging from 5.32 GHz to 8.27 GHz. Thus, acting as directional wideband antenna with total impedance bandwidth of 2.95 GHz (42%). In addition, various geometric parameters of designed antenna have been varied in order to obtain the desired performance. The Proposed antenna has been designed and simulated using 3D finite element based electromagnetic solver HFSS.

Photonic Integrated Multichannel WDM Modulators for Data Read-Out Units

This study presents the recently developed monolithic photonic-integrated circuits that provide efficient amplitude modulation for wavelength division multiplexed optical channels. The circuits were designed for application as a read-out unit in a high-energy physics experiment, and are sufficiently general to be applied in various types of high-speed photonic transmitters. They were constructed using basic building blocks provided in an indium phosphide-based generic integration technology process and fabricated in a multi-project wafer run. Two variants of the circuits, utilizing modulators in Mach-Zehnder and Michelson interferometer configuration, are discussed. A modulation bandwidth of 18.6 GHz was measured and error-free transmission of a 10-Gb/s signal through 85 km of optical fiber was achieved.

A true-time-delay networks design technique

This paper proposes a technique to design wide band switched-line (SL) true-time-delay (TTD) networks, commonly used for phased array antenna (PAA) applications. This study investigates the constant-delay behavior of switched-line phase shifters based on single-pole double-throw (SPDT) switches. Circuit sizing starts by considering the effective S-parameters of the switches, to use their non-idealities as an integral part of the phase shift linearly dependent to the frequency and by considering, from the beginning, the possible spatial positioning of elements that allows the circuit feasibility as a design target. The aim of this study is to provide a technique suitable for the design of well-matched TTD networks with a flat delay in wide bandwidth. In this paper, we propose new design formulas for which we show a single-frequency implementation. A computational strategy is used to obtain numerical solutions of the derived equations with this study. Finally, a monolithic X-band TTD circuit example is shown.

Bio‐signal acquisition circuit with high signal‐to‐noise ratio for u‐healthcare system

The testing of a monolithic bio-signal acquisition circuit with an analogue negative feedback loop for ubiquitous healthcare (u-healthcare) and the monitoring of physical activity is described. The large low-frequency signal is effectively rejected by the proposed circuit, allowing the dynamic range of the more valuable signals to be improved. The proposed circuit has been designed and fabricated using a 0.18 μm 1-poly 6-metal CMOS process. Using an analogue negative feedback loop with a dual-gain filter, the proposed method provides an average signal-to-noise ratio 8.1 dB higher than that of the conventional method.

Ku‐band GaN HPA MMIC with high‐power and high‐PAE performances

A Ku-band high-power and high-power-added efficiency (PAE) high-power amplifier (HPA) monolithic microwave-integrated circuit (MMIC) is demonstrated with a 0.25 μm gallium nitride (GaN) high electron mobility transistor technology on a silicon carbide substrate. Measured continuous-wave performances for the two-stage HPA in-fixture exhibit 17.5-18.3 W of output power ( P OUT ) and 36.4-39.5% of PAE over the frequency range of 13.5-14.5 GHz. The fabricated two-stage HPA MMIC with all matching networks is as small as 3.3 × 3.5 mm, generating an output power density of 1522 mW/mm 2 .

49.1: Flexible Flat‐Panel Display Designs with Gate Driver Circuits Integrated within the Pixel Area

AbstractWe have developed a new stylish TFT‐LCD. We located gate‐driver monolithic circuits in the pixel area. As there are no electronic circuits in the frame area, we can realize a narrow border and round corners or a multi‐concave shape, and the frame shape can be easily revised.

The Role of Substrate Compensation on DC Characteristics of 4H-SiC MESFET with Buffer Layer: A Combined Two-Dimensional Simulations and Analytical Study

An analytical model of 4H-SiC metal semiconductor field effect transistor (MESFET) is proposed with buffer layer on high purity semi-insulating (HPSI) 4H-SiC substrate compensated by multiple deep level traps. The contribution of deep level traps (DLT) is projected and verified using two-dimensional simulations (Silvaco®). The modeled DC characteristics are compared with two-dimensional simulations performed on the same device as considered in the analytical model.The 4H-SiC MESFET is simulated with and without the effect of buffer layer and the electron concentration profiles in different regions are observed from two-dimensional simulations.The electron concentration profiles obtained at channel-substrate interface clearly shows that when the buffer layer is not present, the channel electrons get trapped by the deep level traps used for substrate compensation. It is also observed that the inclusion of buffer layer minimizes the extent of electron trapping by screening out the active channel from the substrate. However, the trapping phenomena take place in both the cases.We believe that the proposed model of 4H-SiC MESFET which includes the substrate compensation through multiple deep level traps may be useful for realizing SiC based monolithic circuits (MMICs) on HPSI substrates.

Proposal for all-graphene monolithic logic circuits

Since the very inception of integrated circuits, dissimilar materials have been used for fabricating devices and interconnects. Typically, semiconductors are used for devices and metals are used for interconnecting them. This, however, leads to a “contact resistance” between them that degrades device and circuit performance, especially for nanoscale technologies. This letter introduces and explores an “all-graphene” device-interconnect co-design scheme, where a single 2-dimensional sheet of monolayer graphene is proposed to be monolithically patterned to form both active devices (graphene nanoribbon tunnel-field-effect-transistors) as well as interconnects in a seamless manner. Thereby, the use of external contacts is alleviated, resulting in substantial reduction in contact parasitics. Calculations based on tight-binding theory and Non-Equilibrium Green's Function (NEGF) formalism solved self-consistently with the Poisson's equation are used to analyze the intricate properties of the proposed structure. This constitutes the first NEGF simulation based demonstration that devices and interconnects can be built using the “same starting material” – graphene. Moreover, it is also shown that all-graphene circuits can surpass the static performances of the 22 nm complementary metal-oxide-semiconductor devices, including minimum operable supply voltage, static noise margin, and power consumption.

Gate-recessed integrated E/D GaN HEMT technology with fT/fmax >300 GHz

We report 1000-transistor-level monolithic circuit integration of sub-30-nm gate-recessed E/D GaN high-electron-mobility transistors with <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fT</i> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> above 300 GHz. Simultaneous <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fT</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> of 348/340 and 302/301 GHz for E- and D-mode devices, respectively, was measured, representing a 58% increase in <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fT</i> compared with our previous report, due to improved management of RC parasitic delay. Three-terminal E- and D-mode breakdown voltage of 10.7 and 11.8 V, respectively, is limited by gate-drain breakdown.

8-channel acquisition system for time-correlated single-photon counting

Nowadays, an increasing number of applications require high-performance analytical instruments capable to detect the temporal trend of weak and fast light signals with picosecond time resolution. The Time-Correlated Single-Photon Counting (TCSPC) technique is currently one of the preferable solutions when such critical optical signals have to be analyzed and it is fully exploited in biomedical and chemical research fields, as well as in security and space applications. Recent progress in the field of single-photon detector arrays is pushing research towards the development of high performance multichannel TCSPC systems, opening the way to modern time-resolved multi-dimensional optical analysis. In this paper we describe a new 8-channel high-performance TCSPC acquisition system, designed to be compact and versatile, to be used in modern TCSPC measurement setups. We designed a novel integrated circuit including a multichannel Time-to-Amplitude Converter with variable full-scale range, a D∕A converter, and a parallel adder stage. The latter is used to adapt each converter output to the input dynamic range of a commercial 8-channel Analog-to-Digital Converter, while the integrated DAC implements the dithering technique with as small as possible area occupation. The use of this monolithic circuit made the design of a scalable system of very small dimensions (95 × 40 mm) and low power consumption (6 W) possible. Data acquired from the TCSPC measurement are digitally processed and stored inside an FPGA (Field-Programmable Gate Array), while a USB transceiver allows real-time transmission of up to eight TCSPC histograms to a remote PC. Eventually, the experimental results demonstrate that the acquisition system performs TCSPC measurements with high conversion rate (up to 5 MHz/channel), extremely low differential nonlinearity (<0.04 peak-to-peak of the time bin width), high time resolution (down to 20 ps Full-Width Half-Maximum), and very low crosstalk between channels.

Gain-Enhanced Monolithic Charge Pump With Simultaneous Dynamic Gate and Substrate Control

This brief presents a gain-enhanced complimentary metal-oxide-semiconductor (CMOS) charge pump (CP) circuit via dynamically controlling the gate and substrate terminals of each pMOS pass transistor. The proposed control strategy enables the CP circuit free of the threshold-voltage drops, the body effect, and the floating substrate terminals of pass devices. The on-resistance of each pass device is also reduced to improve the gain and the power efficiency of the CP circuit. Implemented in a 0.35-μm single n-well CMOS process, the proposed four-stage monolithic CP circuit can operate with a supply voltage down to 0.9 V and deliver a maximum output current of about 100 μA. The proposed CP circuit also achieves a high voltage gain of 4 with two complementary-phase nonoverlapping clock signals.

Image of Monolithic Circuit Segmentation Based on Watershed Algorithm

Abstract. Image segmentation is a key technology in image engineering, it occupy an important position. This paper introduces the watershed transform to Image of monolithic circuit processing method, and then introduced the watershed transform to Image of monolithic circuit segmentation and sample. The results show that, by using the watershed algorithm and morphological processing function, which is connected with a plurality of object images are segmented into a plurality of single object, to achieve the image segmentation, and as far as possible to reduce or eliminate the phenomenon of over-segmentation. Finally it points out the further direction of research.

Dielectric resonator nanoantennas at visible frequencies

Drawing inspiration from radio-frequency technologies, we propose a realization of nano-scale optical dielectric resonator antennas (DRAs) functioning in their fundamental mode. These DRAs operate via displacement current in a low-loss high-permittivity dielectric, resulting in reduced energy dissipation in the resonators. The designed nonuniform planar DRA array on a metallic plane imparts a sequence of phase shifts across the wavefront to create beam deflection off the direction of specular reflection. The realized array clearly demonstrates beam deflection at 633 nm. Despite the loss introduced by field interaction with the metal substrate, the proposed low-loss resonator concept is a first step towards nanoantennas with enhanced efficiency. The compact planar structure and technologically relevant materials promise monolithic circuit integration of DRAs.

Silicon photonic network-on-chip and enabling components

As the transistor’s feature scales down and the integration density of the monolithic circuit increases continuously, the traditional metal interconnects face significant performance limitation to meet the stringent demands of high-speed, low-power and low-latency data transmission for on- and off-chip communications. Optical technology is poised to resolve these problems. Due to the complementary metal-oxide-semiconductor (CMOS) compatible process, silicon photonics is the leading candidate technology. Silicon photonic devices and networks have been improved dramatically in recent years, with a notable increase in bandwidth from the megahertz to the multi-gigahertz regime in just over half a decade. This paper reviews the recent developments in silicon photonics for optical interconnects and summarizes the work of our laboratory in this research field.

Epitaxial top-gated atomic-scale silicon wire in a three-dimensional architecture

Three-dimensional (3D) control of dopant profiles in silicon is a critical requirement for fabricating atomically precise transistors. We demonstrate conductance modulation through an atomic scale 3 nm wide δ-doped silicon–phosphorus wire using a vertically separated epitaxial doped Si:P top-gate. We show that intrinsic crystalline silicon grown at low temperatures (∼250 °C) serves as an effective gate dielectric permitting us to achieve large gate ranges (∼2.6 V) with leakage currents below 1 pA. Combining scanning tunneling lithography for precise lateral confinement, with monolayer doping and low temperature epitaxial overgrowth for precise vertical confinement, we can realize multiple layers of nano-patterned dopants in a single crystal material. These results demonstrate the viability of highly doped, vertically separated epitaxial gates in an all-crystalline architecture with long-term implications for monolithic 3D silicon circuits and for the realization of atomically precise donor architectures for quantum computing.

Integrated wideband and low phase‐noise signal source using two voltage‐controlled oscillators and a mixer

This study presents a method to design a wideband signal source based on two voltage-controlled oscillators (VCOs) with different centre frequencies and a mixer. The principle is to combine three frequency bands to form one wide frequency range. The three bands consist of second harmonic bands from two VCOs and a mixer band that is generated by mixing the two fundamental signals of VCOs to bridge the frequency gap. Apart from the wide tuning range, an additional benefit of a mixer-based signal source is that the phase-noise increases ∼3 dB/octave, which is less than the theoretical limit (6 dB/octave) for a fundamental frequency VCO followed by a frequency multiplier or extraction of second harmonic signal from a VCO. A prototype of the proposed signal source implemented in indium gallium phosphide hetero junction bipolar transistor monolithic microwave integrated circuit technology demonstrates both wide frequency tuning range and a very low phase noise. It exhibits a tuning bandwidth extending from 11.8 to 16.7 GHz and the signal's phase noise varies between −91 and −103 dBc/Hz at 100 kHz offset frequency.

Design and integration of HTS filters with a Josephson device

A high-temperature superconducting (HTS) Josephson frequency down-converting module is demonstrated. An HTS monolithic frequency down-converting circuit and a biasing circuit board for the Josephson device are packaged into the module. The monolithic circuit consists of HTS filters and a Josephson oscillator-mixer device, integrated on a single 10 mm × 20 mm chip of Y Ba2Cu3O7−x (YBCO) film on MgO substrate. A compact, low-loss HTS step-impedance low-pass filter was designed for the intermediate frequency (IF) output port. The modeling, simulation and measurement results of the HTS low-pass filter are presented in this paper. The frequency response and dynamic range of the on-chip integrated HTS down-converting module are also described.

교란 방어를 위하여 히스테리시스가 시리얼로 제어되는 가변 비교기 회로

본 논문에서는 통신, 탐지 및 제어를 위한 원신호의 크기가 시간적으로 변화하고 또한 간섭 잡음의 역할을 하는 교란 신호의 크기도 시간적으로 변화하는 현대전의 상황에서 교란 간섭 신호와 원 신호를 구분하여 원 신호를 디지털신호로 복원하는 확률을 높이기 위하여 본 논문에서는 피드백의 경로에 있는 MOSFET의 실효적인 면적을 디지털 제어 신호로 변경하여 피드백 전류 신호양의 조절하고 히스테리시스의 크기를 조절할 수 있는 IC 회로를 제안하여 설계, 제작 후 측정 및 분석하였다. 병렬 디지털 제어신호에 의한 히스테리시스가 설계 시 예측한 만큼 제어됨을 0.35m-CMOS 공정의 IC 회로를 제작하고 측정하여 증명하였으며 이를 직렬 디지털 제어신호를 제어하기 위한 회로를 설계하여 모의 실험하였다. 또한 교란신호의 크기에 따란 적합한 피드백을 제공하기 위한 제어신호를 모의실험으로 제시하였다. In order to overcome jamming, a hysteresis tunable monolithic comparator circuit based on a 0.35 <TEX>${\mu}m$</TEX> CMOS process is suggested, designed, fabricated, measured and analyzed in this paper. To tune the threshold voltage of the hysteresis in the comparator circuit, two external digital bits are used with supply voltage of 3.3V. An improved variable hysteresis comparator circuit controlled by serial digital bits is suggested, designed and simulated to overcome jamming in modern warfare.