An ultra-high speed monolithic clock recovery circuit in 0.2-µm GaAs process

Abstract

This paper presents a 37 Gb/s phase locked-loop (PLL)-type clock recovery (CR) circuit designed and fabricated in 0.2-µm GaAs PHEMT process. The resonator of the modified LC-VCO is based on a compact circuit topology with high Q-value and better isolation. The active amplifier of the VCO is optimized with a combination of several circuit techniques to reduce phase noise and increase the operation speed. Resonant filters containing high-quality CPWs are employed in the signal preprocessor to accommodate the 37 Gb/s data rate. The measured figure of merit of the modified VCO is about ?196 dBc/Hz at 37-GHz when the PLL is locked. The experimental results also demonstrate that the recovered clock signal of the CR circuit has a phase noise of ?81.66 dBc/Hz at 50 kHz off the center frequency.