A 1.25-Gb/s Burst-Mode Half-Rate Clock and Data Recovery Circuit Using Realigned Oscillation

Abstract

In this letter, a 1.25-Gb/s 0.18-μm CMOS half-rate burstmode clock and data recovery (CDR) circuit is presented. The CDR contains a fast-locking clock recovery circuit (CRC) using a realigned oscillation technique to recover the desired clock. To reduce the power dissipation, the CRC uses a two-stage ring structure and a current-reused concept to merge with an edge detector. The recovered clock has a peak-to-peak jitter of 34.0 ps at 625 MHz and the retimed data has a peak-to-peak jitter of 44.0 ps at 625 Mb/s. The occupied die area of the CDR is 1.4×1.4 mm2, and power consumption is 32 mW under a 1.8-V supply voltage. key words: burst-mode CDR, clock recovery, phase-locked loop, realigned oscillation