A jitter suppression technique for a 2.48832 Gb/s clock and data recovery circuit

Abstract

This paper describes a jitter suppression technique for a 2.48832 Gb/s clock and data recovery (CDR) circuit that uses a phase-locked loop (PLL). This technique improves both the jitter generation and the jitter transfer function. The jitter generation can be suppressed by boosting the loop gain in PLL. A suitable jitter transfer function and jitter tolerance can be achieved by optimizing the characteristics of a surface acoustic wave (SAW) filter. The fabricated circuit had a low jitter generation (about 2.4 mUI rms) and a low jitter transfer function cutoff frequency (about 500 kHz) by using a SAW filter with a center frequency (f/sub c/) of 622.08 MHz. The jitter generations are within f/sub c/ mUI rms for the temperature range between 0/spl deg/C to 90/spl deg/C. The circuit passes the jitter tolerance specification in ITU-T recommendation G.958 by more than 30%.