A jitter suppression technique for a 2.48832-Gb/s clock and data recovery circuit

Abstract

This paper describes a jitter suppression technique for a 2.48832-Gb/s clock and data recovery (CDR) circuit that uses a phase-locked loop (PLL). This technique decreases the jitter generation and improves the jitter transfer function. Jitter generation is suppressed by boosting the loop gain in the PLL. A suitable jitter transfer function and jitter tolerance is achieved by using a low-center-frequency (f/sub c/) surface acoustic wave (SAW) filter. The fabricated circuit has low jitter generation [about 2.4 mUI rms (below 1 ps rms)] and a low cutoff frequency of the jitter transfer function (about 500 kHz) as a result of using a SAW filter with a f/sub c/ of 622.08 MHz. The jitter generations are within 5 mUI rms (2 ps rms) for the temperature range of 0 to 90/spl deg/. The circuit exceeds the jitter tolerance specifications in the International Telecommunication Union (ITU-T) recommendation G.958 by more than 30%.