Monolithic 3D ICs Research Articles

Silicon-based integrated passive device stack for III-V/Si monolithic 3D circuits operating on RF band

In this study, we demonstrated a silicon (Si)-based integrated passive device (IPD) stack to support III-V/Si monolithic 3D (M3D) ICs operating on the radio frequency (RF) band. The IPD stack was fabricated based on an 8-inch CMOS process line and integrated via M3D with an InGaAs HEMT layer. A process condition for a trap rich layer and a buried oxide layer in the IPD was established to simultaneously minimizing both the RF loss and wafer bowing. Through the process condition, the RF loss of the coplanar waveguides was −0.631 dB/mm at 30 GHz, lower than that of the CMOS foundry, and the wafer bowing of the stack was as low as −5.5 μm. The maximum quality factor of the inductors showed good values when compared to those of other CMOS foundry process-based inductors operating on the RF bands reported thus far. To obtain a compressive profile for the IPD stack, which is one of the most important requirements in advancing to wafer-to-wafer-level 3D bonding with the III-V active layer, a process method for the final IMD layer of the IPD was developed, resulting in a change from a tensile profile to a compressive profile for the IPD (corresponding wafer bowing value from −12.6 to + 10.7 μm).

Advancements in single-crystal silicon with elevated-laser-liquid-phase-epitaxy (ELLPE) for monolithic 3D ICs

In this study, we present a low thermal budget elevated-laser-liquid-phase-epitaxy technique designed for the precise fabrication of single-crystal islands (SCIs) intended for use in middle-end-of-line (MEOL) FinFETs. Each of these SCIs features a (100) orientation tended from Si seeding structure and is successfully integrated as channel materials in the MEOL circuit of a monolithic 3D IC (3DIC). This technique effectively mitigates the typical performance disparities associated with poly-Si channel materials in upper tiers, addressing a significant challenge in advanced electronic device fabrication and potentially enhancing the performance and reliability of MEOL FinFETs in monolithic 3DIC.

Modeling and Design of Dual-Purpose MIV in Monolithic 3D IC

Modeling and Design of Dual-Purpose MIV in Monolithic 3D IC

Monitoring time domain characteristics of Parkinson's disease using 3D memristive neuromorphic system.

Parkinson's disease (PD) is a neurodegenerative disorder affecting millions of patients. Closed-Loop Deep Brain Stimulation (CL-DBS) is a therapy that can alleviate the symptoms of PD. The CL-DBS system consists of an electrode sending electrical stimulation signals to a specific region of the brain and a battery-powered stimulator implanted in the chest. The electrical stimuli in CL-DBS systems need to be adjusted in real-time in accordance with the state of PD symptoms. Therefore, fast and precise monitoring of PD symptoms is a critical function for CL-DBS systems. However, the current CL-DBS techniques suffer from high computational demands for real-time PD symptom monitoring, which are not feasible for implanted and wearable medical devices. In this paper, we present an energy-efficient neuromorphic PD symptom detector using memristive three-dimensional integrated circuits (3D-ICs). The excessive oscillation at beta frequencies (13-35 Hz) at the subthalamic nucleus (STN) is used as a biomarker of PD symptoms. Simulation results demonstrate that our neuromorphic PD detector, implemented with an 8-layer spiking Long Short-Term Memory (S-LSTM), excels in recognizing PD symptoms, achieving a training accuracy of 99.74% and a validation accuracy of 99.52% for a 75%-25% data split. Furthermore, we evaluated the improvement of our neuromorphic CL-DBS detector using NeuroSIM. The chip area, latency, energy, and power consumption of our CL-DBS detector were reduced by 47.4%, 66.63%, 65.6%, and 67.5%, respectively, for monolithic 3D-ICs. Similarly, for heterogeneous 3D-ICs, employing memristive synapses to replace traditional Static Random Access Memory (SRAM) resulted in reductions of 44.8%, 64.75%, 65.28%, and 67.7% in chip area, latency, and power usage. This study introduces a novel approach for PD symptom evaluation by directly utilizing spiking signals from neural activities in the time domain. This method significantly reduces the time and energy required for signal conversion compared to traditional frequency domain approaches. The study pioneers the use of neuromorphic computing and memristors in designing CL-DBS systems, surpassing SRAM-based designs in chip design area, latency, and energy efficiency. Lastly, the proposed neuromorphic PD detector demonstrates high resilience to timing variations in brain neural signals, as confirmed by robustness analysis.

An ILD Void Detection Method for Monolithic 3-D ICs Based on Switched Capacitors

Monolithic three-dimensional integrated circuits (M3D ICs) have a higher integration and better performance compared to 3D ICs based on through-silicon vias. However, high integration density and substantial scaling of the inter-layer dielectric (ILD) make M3D ICs extremely prone to occur process defects. In fact, defects such as voids often occur in the bonding process of M3D ICs. Therefore, ILD void detection is necessary in order to achieve high yield for M3D ICs. In this paper, an ILD void detection method based on switched capacitors is proposed. Since voids affect the equivalent capacitance of logic gates above the ILD, voids can be discovered by measuring the gate-level equivalent capacitance. And the value of the capacitance can reflect severity of the void. The effectiveness and accuracy of the proposed method are verified by HSpice simulations. For M3D ICs with the 22 nm process, the minimum capacitance variation identified by this method is 3.355 fF under process variation. And this means nanoscale voids can be detected by the proposed method.

Single-Crystal Germanium by Elevated-Laser-Liquid-Phase-Epitaxy (ELLPE) Technique for Monolithic 3D ICs

This paper proposes and demonstrates single-crystal Germanium (Ge) growth by elevated-laser-liquid-phase-epitaxy (ELLPE) and the fabrication of Ge Fin field-effect transistors (FinFETs) for the monolithic three-dimensional integrated circuits (monolithic 3D ICs). This technique permitted the fabrication of single-crystalline (100) Ge film and FinFETs without random grain boundaries. In comparison with the poly-Ge FinFETs, the ELLPE Ge FinFETs exhibit superior performance and uniformity. Moreover, the ANSYS simulated maximum temperature of bottom circuits during the ELLPE technique does not exceed 400°C, therefore allowing monolithic 3D integration of ICs.

(Invited, Digital Presentation) Heterogeneous IGZO/Si CFET Monolithic 3D Integration

Monolithic 3D-IC is one of the solutions to relieve Moore’s law with vertically integrating circuits for sub-1nm technology nodes. Therefore, thin-film transistors (TFTs) play an important role in this trend because of their low fabrication temperature to realize back-end circuits. On the other hand, 3D integrating filter, duplexer, switch, and so on is necessary as antennas array requirements increase in 5G or beyond. Consequently, it is foreseeable to adopt TFTs to implement radio frequency (RF) devices. Fig. 1 shows the schematic ideal 3D SoC for sub-1nm technology. Our previous research tried to demonstrate high-frequency back-end devices based on the gate-all-around stacked nanosheet low-temperature polycrystalline silicon channel (GAA NS LTPS). Fig.2 shows the current-voltage transfer characteristics of different width designs of LTPS and α-IGZO devices. The only way to enhance GAA NS LTPS RF devices with the same process is by increasing channels. However, it leads to a larger footprint, and the frequency doesn’t boost with increasing channels in proportion because of the capacitance between the multiple channels. In the meantime, the LTPS gate controllability becomes poor, and threshold voltage shifts significantly when the drive current is improved by widening channel width. Consequently, a-IGZO is adopted as the channel material of RF devices to solve the problem mentioned above. The a-IGZO film is back-end compatible and has transparency and high uniformity. The most important is that the gate controllability decay phenomenon is negligible no matter what the channel width is, which is helpful for different width designs. In contrast, IGZO devices can keep their threshold voltage and have ultra-low leakage current due to a large bandgap. According to the system on panel (SoP) trend, we attempt to integrate RFIC with the peripheral circuit on a substrate. Therefore, a-IGZO is also introduced as a pull-down transistor in a CMOS for power reduction and process simplicity. To further minimize the footprint, the a-IGZO devices are nanoscale and stacked on the p-type LTPS as the defined heterogeneous CFET (HCFET), which is demonstrated in the previous study [1]. In this talk, we will discuss HCFET architecture in detail. We compared junctionless mode (JL) and inversion mode (IM) for bottom p-type LTPS in HCFET. In our results, IM is better than JL as the junction structure for bottom PMOS because the requirement of the bottom channel in a HCFET is thin and width flexible for design. In addition, a trench gate of the bottom device plays an important role in HCFET. The trench tri-gate structure can avoid gate dielectric damage by plasma in the etching process, keep the top IGZO layer continuously and enhance performance compared to the general tri-gate structure. On the other hand, the gate of top n-type IGZO can be bottom gate only or dual gate for different requirements. Finally, HCFET can significantly reduce the distance between IGZO and p-type LTPS channels to save power and lower latency in the circuit.[1] S. -W. Chang et al., "First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3-D Integration With Dual Work Function Gate for Ultralow-Power SRAM and RF Applications," in IEEE Transactions on Electron Devices, vol. 69, no. 4, pp. 2101-2107, April 2022, doi: 10.1109/TED.2021.3138947. Figure 1

Generating Brain-Network-Inspired Topologies for Large-Scale NoCs on Monolithic 3D ICs

Network-on-chips (NoCs) with traditional regular topologies generally have an average-hop-count increased, polynomially, with the network size. This brief proposes to generate brain-network-inspired (BNI) topologies on monolithic 3D (M3D) ICs, where the average hop count scales up logarithmically, for large-scale systems with tens of thousands of cores. We propose a routability-driven method to generate BNI topologies on M3D ICs with scale-free and small-world properties. Moreover, we present an iterative method to reduce the network diameter using as few tier-crossing routers as possible. The resulting BNI topologies not only have over 50% lower average hop count and lower diameter than traditional regular topologies, but also have shorter total link length than other irregular topologies. The performance is further validated by the cycle-accurate simulation.

Design Automation and Test Solutions for Monolithic 3D ICs

Monolithic 3D (M3D) is an emerging heterogeneous integration technology that overcomes the limitations of the conventional through-silicon-via (TSV) and provides significant performance uplift and power reduction. However, the ultra-dense 3D interconnects impose significant challenges during physical design on how to best utilize them. Besides, the unique low-temperature fabrication process of M3D requires dedicated design-for-test mechanisms to verify the reliability of the chip. In this article, we provide an in-depth analysis on these design and test challenges in M3D. We also provide a comprehensive survey of the state-of-the-art solutions presented in the literature. This article encompasses all key steps on M3D physical design, including partitioning, placement, clock routing, and thermal analysis and optimization. In addition, we provide an in-depth analysis of various fault mechanisms, including M3D manufacturing defects, delay faults, and MIV (monolithic inter-tier via) faults. Our design-for-test solutions include test pattern generation for pre/post-bond testing, built-in-self-test, and test access architectures targeting M3D.

Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICs

Monolithic 3D (M3D) integration provides massive vertical integration through the use of nanoscale inter-layer vias (ILVs). However, high integration density and aggressive scaling of the inter-layer dielectric make ILVs especially prone to defects. We present a low-cost built-in self-test (BIST) method that requires only two test patterns to detect opens, stuck-at faults, and bridging faults (shorts) in ILVs. We also propose an extended BIST architecture for fault detection, called Dual-BIST, to guarantee zero ILV fault masking due to single BIST faults and negligible ILV fault masking due to multiple BIST faults. We analyze the impact of coupling between adjacent ILVs arranged in a 1D array in block-level partitioned designs. Based on this analysis, we present a novel test architecture called Shared-BIST with the added functionality of localizing single and multiple faults, including coupling-induced faults. We introduce a systematic clustering-based method for designing and integrating a delay bank with the Shared-BIST architecture for testing small-delay defects in ILVs with minimal yield loss. Simulation results for four two-tier M3D benchmark designs highlight the effectiveness of the proposed BIST framework.

Impact of Temperature on Structure Deformation for Monolithic Inter-Tier vias In Monolithic 3D IC Packaging System

The approach of monolithic 3D IC (M3D) integration using monolithic inter-tier-vias (MIVs) as interconnect structures is considered. Although, M3D ICs show many benefits of heterogeneous integration without significant area overhead compared to 3D ICs, reliability and thermal issues become daunting challenges to be addressed. Hence, this study focuses on electromigration issues of current density, thermal stress, and structure deformation due to temperature loading. For the analysis Cu and carbon nanotube (CNT) filler materials were chosen in MIV structure. Our analysis reveals that CNT based MIV offers two-fold higher current density and 91% lesser thermal stress compared to Cu based MIVs. Furthermore, at different voltage values, the current density profiles are examined. For the comprehensive investigations of structure deformations, temperature gradient was allowed at the ends of the MIV structure. The results show less deformations in CNT compared to Cu, based on the stress induced among them. The failure time prediction shows higher mean time to failure value of CNT based MIV than Cu based MIV.

Effects of pre- and post-microwave annealing treatments on pGe MOS device

Effects of pre- and post- microwave annealing (MWA) treatment on electrical characteristics of p-type Ge substrate (pGe) metal-oxide-semiconductor (MOS) devices were investigated in this work. The physical mechanism was studied with an X-ray photoelectron spectroscopy analysis. The pre-MWA treatment, which is similar to conventional post oxidation annealing on interfacial layer (IL), can passivate the oxygen vacancy by chemisorbed oxygen. The excess chemisorbed oxygen atoms may be left at the interface between IL and high-k, which would induce more interface/oxide traps and form more unstable components in IL. The chemisorbed oxygen can be replaced with well-bonded oxygen by using a post-MWA treatment on high-k dielectric , instead of a conventional post deposition annealing. As a result, pGe MOS device with a double-MWA treatment exhibits low equivalent oxide thickness value (~0.65 nm), small frequency dispersion, low interface trap density, and excellent reliability characteristics without increasing the leakage current. The oxygen vacancy passivation and chemisorbed oxygen suppression with a double-MWA treatment are crucial for high performance Ge MOS device and monolithic 3D IC applications. • The effect of pre- and post- microwave annealing (MWA) treatment is compared. • Oxygen vacancy can be passivated by chemisorbed oxygen in pre MWA. • Excess chemisorbed oxygen can be replaced with well-bonded oxygen by post MWA. • A p-type Ge substrate capacitor can be improved by double MWA.

Multi-Tier 3D IC Physical Design with Analytical Quadratic Partitioning Algorithm Using 2D P&R Tool

In this study, we developed a complete flow for the design of monolithic 3D ICs. We have taken the register-transfer level netlist of a circuit as the input and synthesized it to construct the gate-level netlist. Next, we partitioned the circuit using custom-made partitioning algorithms and implemented the place and route flow of the entire 3D IC by repurposing 2D electronic design automation tools. We implemented two different partitioning algorithms, namely the min-cut and the analytical quadratic (AQ) algorithms, to assign the cells in different tiers. We applied our flow on three different benchmark circuits and compared the total power dissipation of the 3D designs with their 2D counterparts. We also compared our results with that of similar works and obtained significantly better performance. Our two-tier 3D flow with AQ partitioner obtained 37.69%, 35.06%, and 12.15% power reduction compared to its 2D counterparts on the advanced encryption standard, floating-point unit, and fast Fourier transform benchmark circuits, respectively. Finally, we analyzed the type of circuits that are more applicable for a 3D layout and the impact of increasing the number of tiers of the 3D design on total power dissipation.

Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Comparisons and Enhancements

Studies have shown that monolithic 3D ( M3D ) ICs outperform the existing through-silicon-via ( TSV ) -based 3D ICs in terms of power, performance, and area ( PPA ) metrics, primarily due to the orders of magnitude denser vertical interconnections offered by the nano-scale monolithic inter-tier vias. In order to facilitate faster industry adoption of the M3D technologies, physical design tools and methodologies are essential. Recent academic efforts in developing an EDA algorithm for 3D ICs, mainly targeting placement using TSVs, are inadequate to provide commercial-quality GDS layouts. Lately, pseudo-3D approaches have been devised, which utilize commercial 2D IC EDA engines with tricks that help them operate as an efficient 3D IC CAD tool. In this article, we provide thorough discussions and fair comparisons (both qualitative and quantitative) of the state-of-the-art pseudo-3D design flows, with analysis of limitations in each design flow and solutions to improve their PPA metrics. Moreover, we suggest a hybrid pseudo-3D design flow that achieves both benefits. Our enhancements and the inter-mixed design flow, provide up to an additional 26% wirelength, 10% power consumption, and 23% of power-delay-product improvements.

Machine Learning Integrated Pseudo-3-D Flow for Monolithic 3-D ICs

Monolithic 3-D (M3-D) IC design is a manufacturing technique that opens several new possibilities of chip design and exploration for power, performance, area (PPA), and cost benefits. Designing a commercially viable M3-D IC first requires a sign-off timing closure capability. Since the commercial tools lack such capability, several 3-D flows have been proposed that treat 3-D as a 2-D die and use commercial 2-D electronic design automation (EDA) tools for the RTL-to-GDS stage. The conversion between the two stages is done late in the design flow and the conversion is also nontrivial. Here, we propose a machine learning-based prediction algorithm to decrease the discrepancy between the pre and post-partitioned 3-D design using regression models. Our proposed model is circuit-agnostic and its performance with respect to a circuit-dependent model is also studied. Furthermore, more details on the behavior and analysis of the model are considered. Overall, we achieve a significant reduction in the total negative slack (TNS) of the test design ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\times $ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$16\times $ </tex-math></inline-formula> ) using the machine learning model integrated pseudo-3-D flow at an expense of just −1%–4% increase in total power.

Monolithic 3D Integrated Circuits: Recent Trends and Future Prospects

Monolithic 3D integration technology has emerged as an alternative candidate to conventional transistor scaling. Unlike conventional processes where multiple metal layers are fabricated above a single transistor layer, monolithic 3D technology enables multiple transistor layers above a single substrate. By providing vertical interconnects with physical dimensions similar to conventional metal vias, monolithic 3D technology enables unprecedented integration density and high bandwidth communication, which plays a critical role for various data-centric applications. Despite growing number of research efforts on various aspects of monolithic 3D integration, commercial monolithic 3D ICs do not yet exist. This tutorial brief provides a concise overview of monolithic 3D technology, highlighting important results and future prospects. Several applications that can potentially benefit from this technology are also discussed.

(Invited) Process Development of CMOS TFTs for Monolithic 3D-IC Applications

Three-dimensional integrated circuit (3D-IC) technology has been used for vertical integration of multi-chip or stacked process in three-dimensional space for the scaling trend of sub-1 nm technical node, in order to overcome the physical limits of electronics and materials in the semiconductor process. Among them, monolithic 3D-IC has many features that can solve the challenge of stacking 2D molds and connecting them in the third dimension. 3D-IC has many significant advantages, such as heterogeneous integration, a smaller footprint but more powerful features, lower costs, reduced power, and higher bandwidth.In this talk, process development of CMOS thin film transistor (TFT) for monolithic 3D-IC will be presented. The channel material of upper layer is the key concern for fabricating device stacked in 3-D space due to the process thermal budget. An amorphous indium gallium zinc oxide (a-IGZO) with activation temperature under 350 ℃ is regarded as the most promising transparent amorphous oxide semiconductor (TAOS) channel material for the advanced TFT device. However, the TAOS TFT is lack of p-channel device. Hence in this work, a top gate poly-Si p-channel TFT (pTFT) device was formed with tri-gate structure by using a self-aligned double patterning (SADP) process. Then, an a-IGZO n-channel TFT (nTFT) based on a bottom gate process were stacked with a monolithic architecture on the same wafer.At first, the process development and optimization of individual AOS nTFT and poly-Si pTFT were carried out. The device structure of AOS nTFT includes a 100 nm-thick TiN metal bottom-gate, 10 nm-thick HfO2 gate dielectric, and IGZO channel. On the other hand, a 100 nm-thick TiN metal top-gate, 10 nm-thick HfO2/ 1 nm-thick SiO2 gate stack, p-type JL poly-Si channel, and tri-gate structure were applied for the poly-Si pTFT. Results show that the on/off current ratio (Ion/Ioff) values of AOS nTFT and poly-Si pTFT are 7 and 6.8 orders, respectively. And the subthreshold swing (S.S.) values are135 and 128 mV/decade, respectively. The device performance of the individual n/p TFTs in this work is similar to that of state-of-the-art devices.Afterwards, hybrid CMOS inverter devices were fabricated and stacked with a monolithic 3D-IC architecture. The Ion/Ioff values of AOS nTFT and poly-Si pTFT are 7.1 and 6.3 orders, respectively. And the S.S. values are135 and 133 mV/decade, respectively. The device performance is quite similar to those of individual n/p TFT fabricated in our group before. Results indicate that the process integration of the AOS nTFT and poly-Si pTFT for monolithic IC is successful. The electrical characteristics of CMOS TFT inverter are pretty good. The voltage gain is ~ 25, the mid voltage is ~ 0.5 Vdd, and the high/low noise margins are large and approximately equal.In order to further improve the performance of nTFT, a novel tungsten (W) dopant was applied to replace gallium (Ga) for ASO film due to its lower price and higher oxygen bond dissociation energy. With higher oxygen bond dissociation energy, the oxygen vacancy can be well controlled and the device may achieve better electrical and reliability characteristics. It is found that the a-IWZO nTFT shows a ION/IOFF value of 7.8 order and a S.S. value of 109 mV/decade. Furthermore, the mobility of a- IWZO TFT is about 2 times higher than that of a-IGZO TFT. The a-IWZO TFT with tiny W dopant as the carrier suppressor can exhibit a smaller S.S. value, suggesting that the channel can be effectively controlled even with higher channel conductivity.To further improve the performance of pTFT, a polycrystalline germanium (poly-Ge) junctionless (JL) TFT is studied. The implantation and activation processes are not required for poly-Ge JL device because the vacancy and interstitial in poly-Ge film can act as acceptors, which naturally turn the film into p-type. However, Ge with poor thermal stability is very sensitive to process temperature. The Ge sub-oxides at Ge surface have lower bandgap, more oxide traps, and interface states, and they may diffuse into gate dielectric after thermal process, resulting in degradation of gate dielectric. The desorption and diffusion of GeOx can be suppressed by nitridation process on interfacial layer (IL) at high-k/Ge. Therefore, in this work, poly-Ge JL pTFT devices with various ILs including GeO2, GeON, O2 plasma-treated HfN, and O2 plasma-treated Al2O3 HfO2 are investigated and compared. The optimal IL for poly-Ge pTFT could be expected. Then, a CMOS device by integrating AOS nTFT and poly-Ge pTFT with a monolithic architecture will be performed as well.

(Invited) Epitaxial Growth of Ge/III-V Films and Hetero-Layer Lift-off for Ultra-Thin GeOI Fabrication

Monolithic 3D (M3D) integration has been thought of as an attractive idea to realize multi-functional heterogeneous integration devices. M3D integration enables us to combine logic devices with different functional devices such as memory, sensor, or optics to create extremely compact and efficient system-on-chips. Ge and III-V compound semiconductors are expected to be implemented as high mobility channel materials and optical components which cannot be realized with Si. The layer transfer technique with low processing temperature has great potential for stacking non-lattice-matched crystalline materials for M3D ICs. Here, we discuss the layer transfer technology utilizing high quality epitaxial growth, low-temperature direct bonding and advanced epitaxial lift-off (ELO) process, which reveals the applicability of transferred layers for heterogeneous integration.The low temperature ELO process is essential for realizing reliable layer transfer with different materials because the process is almost free from the issues of thermal expansion mismatch. Process flow of GaAs or Ge layer transfer with ELO process is described in Fig. 1. First of all, a lattice-matched single crystal GaAs or Ge layer is epitaxially grown on GaAs substrate with an AlAs release layer by MOCVD. Subsequently, Al2O3 layer is deposited on the epitaxial layer by atomic layer deposition (ALD). ALD Al2O3 layer serves as the buried oxide (BOX) and the passivation layer for Ge or GaAs surface. Then, Ge or GaAs layer is patterned using photolithography. The patterned GaAs or Ge/AlAs/GaAs donor wafer is then bonded on host substrate by direct bonding technique with wet activation process. Finally, the epitaxial GaAs or Ge layer is transferred on host substrates by splitting GaAs donor wafer from AlAs layer with HCl side etching thanks to extremely high etching selectivity. Note that the fabrication of patterned transfer layer is effective in shortening the required time of ELO process. In this ELO process, the thickness of a transferred layer can be control by epitaxial layer thickness. After the layer transfer process, the released donor GaAs wafer can be reclaimed and reused for the subsequent re-epitaxial growth to reduce the process cost.Figs. 2 (a) and (b) show cross-sectional SEM and TEM images of fabricated GeOI substrate with different BOX structures. Ge pattern edge shows no peeling from SiO2(100nm)/Si substrate, indicating strong bonding strength at the pattern edge. In Fig. 2 (b), the bonding interface is clearly observed at Al2O3(5nm)/SiO2(50nm) interface formed by the wet activation process. The bonding interface exhibits very smooth and no defect. There is no observable defect in transferred Ge layer, suggesting dislocation density is below TEM detection limit. Compared to Smart-CutTM technique, ELO process has significant advantages in terms of crystal quality, thickness control and the surface flatness thanks to totally low temperature processing.To reduce wafer-scale thickness variation, etching stopper (ES) technique with high etching selectivity is quite useful. As a donor wafer, we prepare Ge active layer (20nm)/SiGe ES layer (5nm)/Ge buffer layer/AlAs/GaAs structures. Here, the SiGe layer serves as ES against the etching of Ge buffer layer to control the final GeOI thickness and attain the wafer-scale thickness uniformity. In addition, Si passivation on Ge surface was performed during initial epitaxial growth of donor wafer since Si passivation was proved to be effective in reducing interfacial trap density (D it) between Ge and oxide. After ELO process, Ge buffer layer /SiGe ES layer/Ge active layer / Al2O3 /SiO2/Si heterostructure was obtained. Then, the top Ge buffer layer was removed in HCl/H2O2 solution. We found the etching selectivity was more than 30 between Ge and SiGe layer, which is high enough to yield very smooth SiGe surface. Finally, SiGe layer was removed by TMAH preferentially.Further conformal thinning of Ge active layer was performed by the cyclic dry oxidation/wet digital etching (DE) at room temperature. In addition to thickness control with the etching rate of about 0.8 nm/cycle, it is found that dozens digital etching (DDE) process is effective for reducing Ge surface roughness. Finally, UTB GeOI substrates with high crystal quality down to 3 nm have been successfully fabricated through SiGe ES and DDE processes. Ultra-smooth GeOI surface with reduced thickness fluctuation was confirmed after DDE by TEM cross-sectional images, resulting in significant improvement of device performances. Figure 1

Impacts of Vertically Stacked Monolithic 3D-IC Process on Characteristics of Underlying Thin-Film Transistor

In this work, the high-performance junctionless-mode (JL) and low-power inversion-mode (IM) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) with nanosheet channels (less than 10-nm in thickness) are vertically integrated in monolithic three-dimensional integrated circuit (3D-IC) structure. Both JL and IM TFTs can exhibit high on/off current ratio over 10 7 to demonstrate their performance. The JL TFT has much higher on-state current ~ 24 times than it of the IM TFT. And the IM-TFT has much lower SS ~ 0.104 V/decade and off-current ~ 0.04 times than them of the JL TFT. However, the fabrication of the top-devices (JL TFTs) would degrade the performance of underlying-devices (IM TFTs), resulting in the threshold voltage shift of the IM TFTs from 0.61 to 2.17 V, SS increase from 0.104 to 0.218 V/decade and on-state current degradation from 16 to 3 mA. In order to further understand the reasons, the IM TFT with top-device removal process is also fabricated, which exhibits a partial recovery in performance. The results indicate the presence and fabrication process of the top-device would lead to the defect generation in the underlying-device. The results provide a new consideration for monolithic 3D-IC manufacturing technology.

Junctionless Poly-GeSn Ferroelectric Thin-Film Transistors with Improved Reliability by Interface Engineering for Neuromorphic Computing

Ferroelectric HfZrOx (Fe-HZO) with a larger remnant polarization (Pr) is achieved by using a poly-GeSn film as a channel material as compared with a poly-Ge film because of the lower thermal expansion that induces higher stress. Then two-stage interface engineering of junctionless poly-GeSn (Sn of ∼5.1%) ferroelectric thin-film transistors (Fe-TFTs) based on HZO was employed to improve the reliability characteristics. With stage I of NH3 plasma treatment on poly-GeSn and subsequent stage II of Ta2O5 interfacial layer growth, the interfacial quality between Fe-HZO and the poly-GeSn channel is greatly improved, which in turn enhances the reliability performance in terms of negligible Pr degradation up to 106 cycles (±2.7 MV/1 ms) and 96% Pr after a 10 year retention at 85 °C. Furthermore, to emulate the synapse plasticity of the human brain for neuromorphic computing, besides manifesting the capability of short-term plasticity, the devices also exhibit long-term plasticity with the characteristics of analog conductance (G) states of 80 levels (>6 bit), small linearity for potentiation and depression of -0.83 and 0.62, high symmetry, and moderate Gmax/Gmin of 9.6. By employing deep neural network, the neuromorphic system with poly-GeSn Fe-TFT synaptic devices achieves 91.4% pattern recognition accuracy. In addition, the learning algorithm of spike-timing-dependent plasticity based on spiking neural network is demonstrated as well. The results are promising for on-chip training, making it possible to implement neuromorphic computing by monolithic 3D ICs based on poly-GeSn Fe-TFTs.