Machine Learning Integrated Pseudo-3-D Flow for Monolithic 3-D ICs

Sai Pentapati,Bon Woong Ku,Sungkyu Lim

doi:10.1109/jxcdc.2021.3095104

Abstract

Monolithic 3-D (M3-D) IC design is a manufacturing technique that opens several new possibilities of chip design and exploration for power, performance, area (PPA), and cost benefits. Designing a commercially viable M3-D IC first requires a sign-off timing closure capability. Since the commercial tools lack such capability, several 3-D flows have been proposed that treat 3-D as a 2-D die and use commercial 2-D electronic design automation (EDA) tools for the RTL-to-GDS stage. The conversion between the two stages is done late in the design flow and the conversion is also nontrivial. Here, we propose a machine learning-based prediction algorithm to decrease the discrepancy between the pre and post-partitioned 3-D design using regression models. Our proposed model is circuit-agnostic and its performance with respect to a circuit-dependent model is also studied. Furthermore, more details on the behavior and analysis of the model are considered. Overall, we achieve a significant reduction in the total negative slack (TNS) of the test design ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\times $ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$16\times $ </tex-math></inline-formula> ) using the machine learning model integrated pseudo-3-D flow at an expense of just −1%–4% increase in total power.

Highlights

M ONOLITHIC 3-D (M3-D) IC design is a process in which multiple dies/tiers are sequentially fabricated on top of each other [1], [2] to create a 3-D die stack
The high bandwidth allows for fine-grained gate-level partitioning of an RTL which can lead to various implementations that target wire length reduction, memory latency reduction, etc
We have analyzed several net features and how they impact the parasitic evolution in a pseudo-3-D flow

Summary

Introduction

M ONOLITHIC 3-D (M3-D) IC design is a process in which multiple dies/tiers are sequentially fabricated on top of each other [1], [2] to create a 3-D die stack. The sequential processing helps one to maintain a 3-D contact pitch ∼100 nm enabling a high connection density and bandwidth between the adjacent dies. The high bandwidth allows for fine-grained gate-level partitioning of an RTL which can lead to various implementations that target wire length reduction, memory latency reduction, etc. A twotiered gate-level 3-D integration has (1/2)× the footprint of a corresponding 2-D design, and (1/(2)1/2)× the linear dimensions. This leads to an average reduction in wire length of up to 30% in a 3-D design

Methods

Results

Conclusion