Monocrystalline Silicon Wafers Research Articles

Fractal analysis on the surface topography of Monocrystalline silicon wafers sawn by diamond wire

The direct impact of diamond wire slicing on the cost of subsequent silicon wafer processing underscores the significance of reducing slicing costs for both the integrated circuit and photovoltaic industries. Effectively and reasonably evaluating monocrystalline silicon wafer quality is thus a crucial challenge. In this paper, fractal theory was used to analyze the monocrystalline silicon wafer sawn surfaces combining with surface roughness measurement. The findings reveal the presence of scratches, pits, and prominent saw marks on the sawn surface. Notably, the surface roughness is significantly higher along the feed direction compared to that along the wire direction. Moreover, an increase in the ratio of feed speed to wire speed leads to a rougher surface. The fractal dimension of the sawn surface is inversely proportional to its roughness, indicating that a higher fractal dimension corresponds to a finer surface texture. Moreover, the two dimensional fractal dimension can effectively capture the anisotropic characteristics of monocrystalline silicon wafers. The two dimensional fractal dimension of the wafer surface obtained by removing materials in ductile mode has a strong symmetry. However, the two dimensional fractal dimension of the surface obtained in brittle mode fluctuates obviously and is weakly symmetric. By combining traditional surface roughness analysis with fractal methods, we can gain insights into the material removal mechanisms involved in slicing monocrystalline silicon wafers using diamond wire, which is of great significance for optimizing diamond wire slicing.

Comparison of Different Approaches to Texturing Monocrystalline Silicon Wafers for Solar Cell Applications

Texturing the surface of crystalline silicon wafers is a very important step in the production of high-efficiency solar cells. Alkaline texturing creates pyramids on the silicon surface, lowering surface reflectivity and improving light trapping in solar cells. This article provides a comparative evaluation of various wet texturing methods using alkaline solutions with or without additives commonly known as surfactants. One method uses sodium hydroxide (NaOH) and isopropyl alcohol (IPA) to create a surface with a height of about 4.5 um by texturing for about 20 minutes, while the other method uses potassium hydroxide (KOH) and other additions known as additives. Texturing was performed using chemicals for only 15 minutes to create a surface shape with a height of approximately 3.5um. Additionally, the two solutions showed reflectance of 8.01% or 12.1% in 400-1100nm, respectively. Both processes used alkaline etching at 80°C for saw damage removal (SDR) before texturing. These processes have also been investigated in terms of removing potential organic contaminants from surfaces. Characterization techniques used throughout the investigation included optical microscopy, surface reflectance measurements, scanning electron microscopy (SEM), and electron dispersive spectroscopy (EDS). The purpose of this study is to confirm through experiments which texturing techniques are more suitable for mass production and to develop time- and cost-effective texturing techniques for industrial production of high-throughput, high-efficiency solar cells.

Controllable Fabrication of Silicon Solar Cells with Inverted or Upright Pyramid Structures by a One-Step Copper Catalysis Method

Silicon has garnered significant attention as the primary material for solar cell preparation. Traditional alkaline etching solutions are limited to creating an upright pyramid structure on monocrystalline silicon surfaces. However, research indicates that an inverted pyramid structure exhibits superior light-trapping properties compared to the upright pyramid structure. In this study, we employed a one-step copper ion metal-assisted chemical etching process to fabricate an inverted pyramid structure on monocrystalline silicon wafers. This method allows for the customization of either inverted or upright pyramid structures by adjusting the concentration of specific solution components. Characterization of the textured silicon wafers reveals that the inverted pyramid structure exhibits lower reflectivity than both the upright pyramid structure and polished silicon. By integrating this texturing technique into the solar cell production line, we successfully produced solar cells with both inverted and upright pyramid structures. Evaluation of various solar cell parameters demonstrates that the inverted pyramid structure outperforms the upright pyramid structure, showcasing lower reflectivity and higher photoelectric conversion efficiency.

Effect of Polyoxyethylene-Based Nonionic Surfactants on Chemical–Mechanical Polishing Performance of Monocrystalline Silicon Wafers

Effect of Polyoxyethylene-Based Nonionic Surfactants on Chemical–Mechanical Polishing Performance of Monocrystalline Silicon Wafers

Surface topography and subsurface structure evolution in laser micro polishing of monocrystalline silicon

Ultra-smooth silicon surfaces, crucial in short-wave optics, can be marred by surface defects and subsurface damage incurred during machining, thereby affecting the imaging quality and transmission efficiency of optical components. Laser micro-polishing emerges as a versatile and efficient technique for ultra-precision polishing. This study aims to scrutinize the surface topography and subsurface structural evolution of monocrystalline silicon wafers during laser micro-polishing experimentally and to formulate an accessible evaluation model that incorporates multiple process parameters for optimal polishing results. As laser fluence escalates, the polishing process can be divided into six regimes: bulge, coalescence, smoothness, groove, ripple, and ablation. Each regime's crystal structure evolution is analyzed using Raman spectroscopy, demonstrating a close relationship with the surface expansion preceding the melting of monocrystalline silicon. Surface roughness diminishes from 6 nm to 0.7 nm, and an optimal crystalline quality devoid of an amorphous layer, residual stress, or significant subsurface damage is achieved. Amorphous silicon, 20 μm thick, is converted into monocrystalline silicon through recrystallization, and subsurface distortions and dislocations are rectified due to silicon atom redistribution. Moreover, a mapping relationship between multiple process parameters and surface polishing effects is established. A dimensionless fluence considering multiple parameters is derived, and a predictive model for process parameter optimization to secure optimal polishing results is proposed.

Dislocation determination and quality control of industrial casting monocrystalline silicon

By analyzing dislocation ratio data of casting monocrystalline silicon wafers and photovoltaic conversion efficiency of the fabricated solar cells and comparing analyzing growth height and dislocation ratio of silicon crystalline, we derived the calculation equation of dislocation growth in the vertical direction. According to this, the determination software for the dislocation area of casting monocrystalline silicon blocks has been developed, and we realized the adequate delineation and interception of serious dislocation area in casting monocrystalline silicon blocks. The batch conversion efficiency gap between the casting monocrystalline silicon and the Czochralski (CZ) monocrystalline silicon has been narrowed from 0.51 % to 0.19 %, and the low efficiency ratio of casting monocrystalline silicon cells has been reduced from 6.98 % to 0 %. Finally, the stability and competitiveness of casting monocrystalline silicon wafer products have been improved.

Photocatalysis of silicon nanowires decorated with metallic nanoparticles and graphene oxide under different light intensities

This work shows silicon nanowires (SiNWs), decorated with different nanoparticles, as a photocatalytic material under different lighting conditions. In this system, the comparison between different materials and the influence of light intensity on their performances are studied. On the other hand, the synthesis of SiNWs was done by a metal-assisted chemical etching. The decoration with nanoparticles of copper CuNPs and cuprous oxide CuO2NPs was conducted with the electroless technique. Graphene oxide (GO) lamellar particles passing through an atmospheric pressure plasma (APPJ) were instantaneously ionized losing OH radicals and connecting them into a continuous coating around the SiNWs nanostructures. Such a layer with a large contact area among SiNWs/GO/Cu/CuO2 was obtained with a small thickness of about 10–20 nm. This is proposed to allow and increase charge carrier transference to the aqueous solution for redox reactions to degrade the dye molecules. Through statistical analysis, we compared the percentages of the decrease in methyl orange concentration used to measure the photocatalytic performance. SiNWs – CuNPs surfaces, in combination with high-intensity light, exhibit higher degradation percentages and rate constants. The graphene oxide coatings were deposited on monocrystalline silicon wafers and silicon nanowires, constituting a semiconductor-semiconductor heterojunction. This is an innovation proposed in this work that could lead to the fabrication of semiconductor heterojunctions with Z-scheme complementarity.

Electrophysical parameters of p-i-n photodiodes, irradiated with 60Co γ-quanta

The results of studies of changes in the electrical parameters of p-i-n photodiodes manufactured on monocrystalline silicon wafers of p-type conductivity orientation (100) with ρ = 1000 Ohm cm, when irradiated with γ-quanta from a 60Co source, are presented. It has been established that as a result of irradiation of p-i-n photodiodes with doses up to 2·1015 quanta/cm2, the reverse dark current increases by more than an order of magnitude. However, the shape of the curve of the dependence of the current on the applied reverse voltage of irradiated p-i-n photodiodes does not change qualitatively, as for the original devices there are three regions with different dependences of current on voltage: sublinear, superlinear and linear, due to different mechanisms of generation-recombination processes in the depletion region of the p-n junction. The main reason for the increase in the reverse current of p-i-n photodiodes as a result of irradiation with γ-quanta is the formation of generation-recombination centers of radiation origin due to the condensation of primary radiation defects (vacancies and/or self-interstitial atoms) on technological residual structural defects formed during the growth of silicon single crystals, and during subsequent high-temperature treatments during the formation of devices.

Multi-objective optimization of energy consumption, surface roughness, and material removal rate in diamond wire sawing for monocrystalline silicon wafer

Multi-objective optimization of energy consumption, surface roughness, and material removal rate in diamond wire sawing for monocrystalline silicon wafer

Slurry pressure at the cutting zone in multi-wire sawing: An experimental study

Multi-wire sawing has been widely used in the processing of semiconductor material wafers employed in integrated circuits, solar cells, etc. Recently, free abrasive multi-wire sawing has been gradually replaced by solid abrasive multi-wire sawing technology in the domain of solar wafers. However, free abrasive sawing still plays an important role in the processing of electronic-grade monocrystalline silicon wafers, where the requirements on the wafer quality are continuously increasing. Because the free abrasive multi-wire sawing process is very complex, its material removal mechanisms are not fully understood. In this study, experiments were designed to measure the slurry pressure at the cutting zone during a free abrasive multi-wire sawing process to fabricate monocrystalline silicon wafers, and the pressure distribution condition throughout the cutting zone was obtained. Two sets of micropores of 0.17 mm diameter were processed on the experimental workpiece to transmit the cutting zone fluid pressure to the sensor. Each group of micropores consisted of 17 small pores, divided into three rows, with the row spacing consistent with the pitch width of the wire guide. During installation, the center line of each row of micropores was aligned with the center line of the steel wire. The pressure at the cutting zone was measured using the micropores to transfer the slurry pressure to the sensor. Calibration experiments were conducted by considering the capillary effects of the micropores, and the actual pressure at the cutting zone was obtained. Experimental results show that the slurry pressure was 0.16 bar at 40 mm near the slurry inlet. As the distance from the slurry inlet increased, the pressure fluctuated around 0.14 bar. Furthermore, at a distance of 160 mm from the slurry inlet, the sensor was not able to detect the pressure at the cutting zone. The experimental results from the free abrasive multi-wire sawing pressure measurement showed that material removal involves a three-body action comprising the metal wire, abrasive grains, and workpiece. At the cutting zone far from the location of the slurry inlet, forming a stable and continuous film with the slurry is difficult. The experimental results confirm that the force of material removal during the sawing process mainly comes from the wire tension of the steel wire. The film thickness of the slurry in the cutting zone is determined by the diameter of the abrasive between the wire and ingot. The experimental conclusion is of great significance for understanding the complex material removal process in the cutting zone for multi-wire sawing.

Silicon wafer bonding by the glass-like sol-gel formed nanocomposite

We have herein developed a glass-forming composition and the related sol-gel technology for bonding monocrystalline silicon wafers to produce «silicon–insulator–silicon» structures. A possibility to fabricate defect-free glass-like bonding layers at the annealing temperature decreased to 1000–1100 °C is demonstrated. The composites obtained by the sol-gel method can be used in technological processes of formation of the solid compound of silicon wafers.

Effect of the diamond saw wires capillary adhesion on the thickness variation of ultra-thin photovoltaic silicon wafers during slicing

In order to improve the performance of solar cells and reduce their manufacturing costs, monocrystalline silicon wafers used for manufacturing solar cells are developing towards larger sizes and ultra-thin thickness, and the diameter of diamond saw wires used to cut silicon wafers is also continuously decreasing. These aspects cause uneven thickness and lager thickness variation (TV) of the as-cut wafer during slicing process. The reason of uneven thickness was analyzed from the point of liquid bridge with capillary force between the saw wires in this paper. The mechanical equilibrium equation between the liquid bridge and the saw wires was established based on the Young-Laplace equation, and the theoretical model of the as-cut wafer thickness was derived during the sawing process. The effect of the saw wire tensioning force, span, the diameter of the core wire and the wetting angle of coolant on the as-cut wafer thickness variation was analyzed based on the model. The results show that the increase in the saw wire tensioning force, the core wire diameter and the wetting angle of coolant improved the thickness accuracy and reduced the thickness variation of the as-cut wafer. And the increase in the saw wire span reduced the thickness accuracy and increased the thickness variation. The research results of this paper provide the mechanism analysis for the thickness variation of the ultra-thin wafer during the slicing process. It is of great significance to produce the ultra-thin photovoltaic silicon wafers with the fine saw wire in the future.

Textured p-type crystalline silicon surfaces obtained by multi-step plasma process for SHJ solar cells

P-type monocrystalline silicon wafers were textured by means of a multi-step plasma etching technique with the aim of greatly reducing their reflectance and effectively exploiting the highest possible amount of solar radiation in heterojunction photovoltaic devices. Suitable surface morphologies, characterized by high light scattering, have to be obtained without damaging the c-Si electrical properties. For this reason, some aspects of the plasma etching process have been studied and improved. Modifications have been made to obtain both “cleaner” processes and energetically lower ion bombardment. By operating at high pressure (0.4 mbar), a process controlled by diffusion of reactive species towards the substrate was favoured. Another innovative aspect consisted in two “reconditioning” plasma processes of the Si surface before the actual silicon removal step with SF6 /O2 gas mixtures. A strong reduction in the average optical reflection down to 5% was obtained coupled with a minority carriers lifetime (τeff) of about 950 μs, value comparable to that of the untreated silicon. An interesting surface morphology, consisting in “U" shaped cavities, was obtained. Texture irregularities were easily removed by acid etching. The moderate depth of the cavities is very promising for an effective passivation with a-Si:H thin films.

Impacts of Wafer Doping Type on Structural and Optical Properties of Black Silicon Fabricated by Metal-Assisted Chemical Etching

In this work, the impacts of wafer doping type on structural and optical properties of black silicon (b-Si) fabricated by metal-assisted chemical etching (MACE) process are investigated. P-type and n-type mono-crystalline silicon (mono c-Si) wafers are etched in an aqueous solution of hydrofluoric acid (HF), silver nitrate (AgNO3) and deionised water (DI H2O) at room temperature and various durations from 5-20 minutes. Surface morphological results demonstrate the formation of b-Si nanowires (NWs) with average lengths of 0.4-0.8 μm for p-type wafers and 0.8-3.0 μm for n-type wafers. The higher length of the NWs for the n-type wafers is due to the minority charge carriers, which lead to a higher etching rate during the MACE process. Within the 300-1100 nm wavelength region, weighted average reflection (WAR) for the p-type and n-type wafers decreases to 6.6% and 6.4%, respectively, after 20 minutes of etching. The corresponding improvement in broadband light absorption results in maximum potential short-circuit current density (Jsc (max)) of 38.2 and 38.8 mA/cm2 for the p-type and n-type b-Si, respectively, which is an of enhancement of 39.9% and 42.1% when compared to the Jsc (max) of planar c-Si reference.

Heterogeneous Photocatalysis using Electroless Deposition of Ni/NiO Nanoparticles on Silicon Nanowires for the Degradation of Methyl Orange

Aims: This work uses the MACE method to synthesize SiNWs- NiNPs/NiONPs to degrade organic pollutants by photocatalysis. Background: Photocatalytic degradation has been applied as an attractive solution to remove several organic pollutants. Heterostructured nanomaterials have become an interesting platform for investigation. Metal-assisted chemical etching (MACE) stands out as a promising technique because it is simple, low cost, and fast. Objective: Attain the degradation of methyl orange (MO) in the presence of silicon nanowires (SiNWs) in heterojunction with Nickel/Nickel Oxide nanoparticles (NiNPs-NiONPs). Methods: SiNWs were synthesized by metal (Ag) assisted chemical etching (MACE) of monocrystalline silicon wafers. NiNPs were non-electrolytically deposited on the SiNWs (electroless method). The morphology of the SiNWs- NiNPs/NiONPs was observed by SEM. Results: Heterogeneous photocatalytic degradation of methyl orange (C14H14N3NaO3S) in an aqueous solution at a concentration of 20 ppm had an efficiency of 66.5% after 180 min under UV irradiation. The MO degradation percentage was determined using UV-visible spectrophotometry. Conclusion: The SiNWs-NiNPs/NiONPs were obtained composed mainly of Si covered by SiO2 decorated on the tips with Ni (II) in the form of NiO and a small amount of nickel metal. The removal efficiency obtained at 180 min of light exposure was 66.5%. After the photocatalysis tests, further oxidation of the NiNPS into NiONPS, was attributed to the reactive oxygen species in the aqueous medium based on the changes of the oxygen and Ni2p3/2 peaks by XPS. Other: Through XPS, the oxidation state of the SiNWs- NiNPs/NiONPs was analyzed.

Effect of High-Temperature Annealing on Raman Characteristics of Silicon Nanowire Arrays

We demonstrate two distinct experimental processes involving the large-area growth of ordered and disordered silicon nanowire arrays (SiNWs) on a p-type silicon substrate using the metal-assisted chemical etching method. The two processes are based on the etching of monocrystalline silicon wafers by randomly distributed Ag films and ultra-thin Au films with ordered nano-mesh arrays, respectively, wherein the growth of SiNWs is implemented using a specific proportion of a HF-containing solution at room temperature. In this study, the microstructural change mechanisms for the two morphologically different arrays before and after annealing were investigated using Raman spectra. The effects of various mechanisms on the observed Raman scattering peak’s deviation from symmetry, redshift and broadening were analyzed. The evolution of the unstable amorphous structures of nanoscale materials during the high-temperature annealing process was observed via high-resolution scanning electron microscope (SEM) observations. The scattering peak parameters determined from the Raman spectra led to conclusions concerning the various mechanisms by which high-temperature annealing influences the microstructures of the two morphologically different SiNWs fabricated on the p-type silicon substrate. Therefore, the deviation of SiNWs from the monocrystalline silicon scattering peak at 520.05 cm−1 when changing the diameter of the nanowire columns was calculated to further analyze the effect of thermal annealing on Raman characteristics.

Study on the temperature field in the cutting zone for machining monocrystalline silicon wafer using free abrasive multi-wire saw

With increasing applications of integrated circuits, the requirements for the quality of the corresponding substrate silicon wafers have become more stringent. Slicing is a key step in the manufacturing of silicon wafers. At present, free-abrasive multi-wire saw (MWS) technology is commonly employed for substrate silicon wafer processing. However, the actual temperature field in the cutting zone is unclear because of the narrow cutting zone in multi-wire sawing. Although a simulation method was adopted in this study, the distribution of the slurry in the cutting zone remains ambiguous, causing a large difference between the simulation results. The temperature field is an important cause of warpage, which significantly affects wafer quality. In this study, an experiment and simulation of the temperature field in the cutting zone of a MWS of monocrystalline silicon with free abrasives were performed. First, an experiment was designed to measure the temperatures at different positions in the cutting zone. Then, based on the experimental data of the fluid pressure distribution and the temperature field in the cutting zone, after obtaining the heat source model, a simulation analysis was conducted, and the results are consistent with the experimental results. Finally, based on the heat flux model, the temperature field distribution in the cutting zone under different cutting conditions was simulated and analyzed. Temperatures of 36.7, 39.4, 40.7, and 42.8 °C were obtained at 22.5, 62.5, 137.5, and 177.5 mm, respectively, from the slurry entrance in the cutting zone. According to the heat source model based on the pressure distribution data of slurry in the cutting zone, the temperature values obtained via simulation at 22.5, 62.5, 137.5, and 177.5 mm from the slurry inlet were 35.4, 37.4, 41.5, and 43.1 °C, respectively. The maximum temperature difference is 1.8K°C, and the average temperature difference is 0.2K°C. Thus, the validity of the heat source model was verified. Further, based on the heat source model, the maximum temperature for cutting a 300-mm monocrystalline silicon wafer was predicted as 48.4 °C. Moreover, the wire speed was found to greatly influence the maximum temperature in the cutting zone. Tension also affects the temperature of the cutting zone, but to a lesser extent than the wire speed.

Study of the Enhanced Efficiency of Crystalline Silicon Solar Cells by Optimizing Anti Reflecting Coating using PC1D Simulation

In this paper, simulation of a mono crystalline silicon solar cell was done using PC1D software. The impact of different solar cell parameters, with their effects on power and efficiency, has been investigated. It is seen that the textured surface reduces reflection and increases the efficiency of the solar cell at least 2–3%. From the simulation, it is seen that the optimum value of p-type doping concentration 1 × 10^16 cm^−3, n-type doping concentration 5 × 10^18 cm with pyramid height of 2–3 μm and equal angles of 54.74 degrees produces the best result in simulation. An anti-reflective coating with a refractive index of 1.38 and a thickness of 84 nm is considered optimal. By optimizing the effective parameters, a solar cell with an efficiency of 24.45% was achieved through simulation. For a p-type mono crystalline silicon wafer, with an area of 10 × 10 cm^2 and a thickness of 200 μm, initial simulation shows a 24.45% efficient solar cell.

Fabrication of N-Type Nanocrystalline Silicon Thin-Film by Magnetron Sputtering and Antimony Induced Crystallization

The fabrication of n-type nanocrystalline silicon thin films using magnetron sputtering and crystallization by adding antimony and thermal treatment is presented in this article. Firstly, a short overview about thin film deposition methods, along with the advantages and disadvantages of the magnetron sputtering, is provided. Then, the technique of adding metals for recrystallization of amorphous silicon is described, and the necessity of using antimony for obtaining n-type nanocrystalline silicon along with its characteristics is discussed. Next, the process of thin film deposition using magnetron sputtering and the production of n-type nanocrystalline silicon on a quartz substrate, by antimony induced crystallization, is explained. Subsequently, the characterization process and necessary measurements to confirm the crystallization of the nanocrystalline silicon layer and determine its crystalline properties are presented. For ease of electrical characterization, a simple n/p junction Schottky solar cell is fabricated using the produced nanocrystalline silicon layer on a p-type monocrystalline silicon wafer. In addition to nanocrystalline properties, the optical and electrical characteristics of this cell are also investigated. The measurements show that with the proposed method, a fine grains nanocrystalline silicon layer with an average grain size of 20 nm was formed in the <111> direction. J-V characteristic measurement shows the creation of a solar cell with conversion efficiency of 1.39%, open circuit voltage of 265mV and current density of 16.32mA/cm2. These results confirm that antimony can be used in the process of crystallizing amorphous thin film silicon obtained from magnetron sputtering and converting it into n-type nanocrystalline silicon.

Modeling and experimental investigation of monocrystalline silicon wafer cut by diamond wire saw

Diamond wire sawing is one of the key technologies in solar cell manufacturing process and semiconductor chip manufacturing process. The thinned of silicon wafer has become a development trend of semiconductor industry, and the reduction of silicon wafer thickness can improve the material utilization and reduce the manufacturing cost. Therefore, the minimum thickness analytical model of diamond wire saw cutting monocrystalline silicon wafer is proposed in this paper to study the processing mechanism of minimum thickness of monocrystalline silicon wafer. Firstly, based on the Kirchhoff’s thin plate theory, the theoretical equation of the maximum internal stress of single silicon wafer and the sawing thickness of the silicon wafer is derived from the sawing force model. Combined with the Mohr’s strength theory, the analytical model of minimum sawing thickness of monocrystalline silicon wafer is established. Then, the analytical model is verified by the finite element simulation. The average error between the simulation results and the calculation results of the analytical model about the minimum sawing thickness of silicon wafer is 9%. Finally, the monocrystalline silicon sawing verification experiments are conducted under some groups of processing conditions. The experimental results show that the minimum sawing thickness of the silicon wafer decreases with the increasing axial speed of the wire saw, increases with the increase of the feed rate of the wire saw, and decreases first and then increases with workpiece speed becoming large. The average error of the experimental results and the calculation results of the analytical model of the wafer minimum sawing thickness is 7.4%, which verifies corrections of the analytical model.