Monocrystalline Silicon Wafers Research Articles

Effect of High-Temperature Annealing on Raman Characteristics of Silicon Nanowire Arrays

We demonstrate two distinct experimental processes involving the large-area growth of ordered and disordered silicon nanowire arrays (SiNWs) on a p-type silicon substrate using the metal-assisted chemical etching method. The two processes are based on the etching of monocrystalline silicon wafers by randomly distributed Ag films and ultra-thin Au films with ordered nano-mesh arrays, respectively, wherein the growth of SiNWs is implemented using a specific proportion of a HF-containing solution at room temperature. In this study, the microstructural change mechanisms for the two morphologically different arrays before and after annealing were investigated using Raman spectra. The effects of various mechanisms on the observed Raman scattering peak’s deviation from symmetry, redshift and broadening were analyzed. The evolution of the unstable amorphous structures of nanoscale materials during the high-temperature annealing process was observed via high-resolution scanning electron microscope (SEM) observations. The scattering peak parameters determined from the Raman spectra led to conclusions concerning the various mechanisms by which high-temperature annealing influences the microstructures of the two morphologically different SiNWs fabricated on the p-type silicon substrate. Therefore, the deviation of SiNWs from the monocrystalline silicon scattering peak at 520.05 cm−1 when changing the diameter of the nanowire columns was calculated to further analyze the effect of thermal annealing on Raman characteristics.

Study on the temperature field in the cutting zone for machining monocrystalline silicon wafer using free abrasive multi-wire saw

With increasing applications of integrated circuits, the requirements for the quality of the corresponding substrate silicon wafers have become more stringent. Slicing is a key step in the manufacturing of silicon wafers. At present, free-abrasive multi-wire saw (MWS) technology is commonly employed for substrate silicon wafer processing. However, the actual temperature field in the cutting zone is unclear because of the narrow cutting zone in multi-wire sawing. Although a simulation method was adopted in this study, the distribution of the slurry in the cutting zone remains ambiguous, causing a large difference between the simulation results. The temperature field is an important cause of warpage, which significantly affects wafer quality. In this study, an experiment and simulation of the temperature field in the cutting zone of a MWS of monocrystalline silicon with free abrasives were performed. First, an experiment was designed to measure the temperatures at different positions in the cutting zone. Then, based on the experimental data of the fluid pressure distribution and the temperature field in the cutting zone, after obtaining the heat source model, a simulation analysis was conducted, and the results are consistent with the experimental results. Finally, based on the heat flux model, the temperature field distribution in the cutting zone under different cutting conditions was simulated and analyzed. Temperatures of 36.7, 39.4, 40.7, and 42.8 °C were obtained at 22.5, 62.5, 137.5, and 177.5 mm, respectively, from the slurry entrance in the cutting zone. According to the heat source model based on the pressure distribution data of slurry in the cutting zone, the temperature values obtained via simulation at 22.5, 62.5, 137.5, and 177.5 mm from the slurry inlet were 35.4, 37.4, 41.5, and 43.1 °C, respectively. The maximum temperature difference is 1.8K°C, and the average temperature difference is 0.2K°C. Thus, the validity of the heat source model was verified. Further, based on the heat source model, the maximum temperature for cutting a 300-mm monocrystalline silicon wafer was predicted as 48.4 °C. Moreover, the wire speed was found to greatly influence the maximum temperature in the cutting zone. Tension also affects the temperature of the cutting zone, but to a lesser extent than the wire speed.

Study of the Enhanced Efficiency of Crystalline Silicon Solar Cells by Optimizing Anti Reflecting Coating using PC1D Simulation

In this paper, simulation of a mono crystalline silicon solar cell was done using PC1D software. The impact of different solar cell parameters, with their effects on power and efficiency, has been investigated. It is seen that the textured surface reduces reflection and increases the efficiency of the solar cell at least 2–3%. From the simulation, it is seen that the optimum value of p-type doping concentration 1 × 10^16 cm^−3, n-type doping concentration 5 × 10^18 cm with pyramid height of 2–3 μm and equal angles of 54.74 degrees produces the best result in simulation. An anti-reflective coating with a refractive index of 1.38 and a thickness of 84 nm is considered optimal. By optimizing the effective parameters, a solar cell with an efficiency of 24.45% was achieved through simulation. For a p-type mono crystalline silicon wafer, with an area of 10 × 10 cm^2 and a thickness of 200 μm, initial simulation shows a 24.45% efficient solar cell.

Fabrication of N-Type Nanocrystalline Silicon Thin-Film by Magnetron Sputtering and Antimony Induced Crystallization

The fabrication of n-type nanocrystalline silicon thin films using magnetron sputtering and crystallization by adding antimony and thermal treatment is presented in this article. Firstly, a short overview about thin film deposition methods, along with the advantages and disadvantages of the magnetron sputtering, is provided. Then, the technique of adding metals for recrystallization of amorphous silicon is described, and the necessity of using antimony for obtaining n-type nanocrystalline silicon along with its characteristics is discussed. Next, the process of thin film deposition using magnetron sputtering and the production of n-type nanocrystalline silicon on a quartz substrate, by antimony induced crystallization, is explained. Subsequently, the characterization process and necessary measurements to confirm the crystallization of the nanocrystalline silicon layer and determine its crystalline properties are presented. For ease of electrical characterization, a simple n/p junction Schottky solar cell is fabricated using the produced nanocrystalline silicon layer on a p-type monocrystalline silicon wafer. In addition to nanocrystalline properties, the optical and electrical characteristics of this cell are also investigated. The measurements show that with the proposed method, a fine grains nanocrystalline silicon layer with an average grain size of 20 nm was formed in the <111> direction. J-V characteristic measurement shows the creation of a solar cell with conversion efficiency of 1.39%, open circuit voltage of 265mV and current density of 16.32mA/cm2. These results confirm that antimony can be used in the process of crystallizing amorphous thin film silicon obtained from magnetron sputtering and converting it into n-type nanocrystalline silicon.

Modeling and experimental investigation of monocrystalline silicon wafer cut by diamond wire saw

Diamond wire sawing is one of the key technologies in solar cell manufacturing process and semiconductor chip manufacturing process. The thinned of silicon wafer has become a development trend of semiconductor industry, and the reduction of silicon wafer thickness can improve the material utilization and reduce the manufacturing cost. Therefore, the minimum thickness analytical model of diamond wire saw cutting monocrystalline silicon wafer is proposed in this paper to study the processing mechanism of minimum thickness of monocrystalline silicon wafer. Firstly, based on the Kirchhoff’s thin plate theory, the theoretical equation of the maximum internal stress of single silicon wafer and the sawing thickness of the silicon wafer is derived from the sawing force model. Combined with the Mohr’s strength theory, the analytical model of minimum sawing thickness of monocrystalline silicon wafer is established. Then, the analytical model is verified by the finite element simulation. The average error between the simulation results and the calculation results of the analytical model about the minimum sawing thickness of silicon wafer is 9%. Finally, the monocrystalline silicon sawing verification experiments are conducted under some groups of processing conditions. The experimental results show that the minimum sawing thickness of the silicon wafer decreases with the increasing axial speed of the wire saw, increases with the increase of the feed rate of the wire saw, and decreases first and then increases with workpiece speed becoming large. The average error of the experimental results and the calculation results of the analytical model of the wafer minimum sawing thickness is 7.4%, which verifies corrections of the analytical model.

Breakage Ratio of Silicon Wafer during Fixed Diamond Wire Sawing.

Monocrystalline silicon is an important material for processing electronic and photovoltaic devices. The fixed diamond wire sawing technology is the first key technology for monocrystalline silicon wafer processing. A systematic study of the relationship between the fracture strength, stress and breakage rate is the basis for thinning silicon wafers. The external vibration excitation of sawing machine and diamond wire lead to the transverse vibration and longitudinal vibration for silicon wafers. The transverse vibration is the main reason of wafer breakage. In this paper, a mathematical model for calculating breakage ratio of silicon wafer is established. The maximum stress and breakage ratio for as-sawn silicon wafers are studied. It is found that the maximum amplitude of the silicon wafers with the size of 156 mm × 156 mm × 0.2 mm was 160 μm during the diamond wire sawing process. The amplitude, maximum stress and breakage rate of the wafers increased with the increase of the cutting depth. The smaller the silicon wafer thickness, the larger of silicon wafer breakage ratio. In the sawing stage, the breakage ratio of the 156 mm × 156 mm section with a thickness of 0.15 mm of silicon wafers is 6%.

Enhanced Anticorrosion and Antifouling Properties of Lubricant‐Infused Pyramidal Polydimethylsiloxane Coating

AbstractAlthough slippery liquid‐infused porous surfaces (SLIPSs) have been extensively studied for anticorrosion and antifouling applications, their durability and stability restrict their practicality. Herein, a technique is presented for fabricating SLIPS with dual‐protection. First, a polydimethylsiloxane (PDMS) coating with a pyramidal morphology is fabricated through mold‐based lithographic techniques. The mold is prepared by applying a texturing process to a monocrystalline silicon wafer of the type used to produce solar cells. Once infused with lubricant, the SLIPS is prepared and has a water‐contact angle of 112°, on an inclined surface, water droplets slide easily off its surface. Due to the excellent chemical stability and low superficiality of the lubricant layer, the SLIPS offers excellent antifouling and anticorrosion properties. In a static marine environment, the SLIPS has an extremely low coverage fraction of algae. After being immersed in a 3.5% NaCl solution for 400 days, |Z|0.01 Hz ≈ 1011 Ω, and the phase angle at high frequency is approximately −90°. SLIPSs based on the PDMS coating provide dual protection (anticorrosion and antifouling), showing that this design approach produces SLIPSs with excellent potential for applications in marine environments.

Inverted pyramid structure on monocrystalline silicon processed by wet etching after femtosecond laser machining in air and deionized water

The micro-structured silicon has been preliminarily applied to improve the surface and optical properties of micro-solar cells, micro-optical systems, and aerospace engineering. However, the morphological changes and optical properties of monocrystalline silicon during femtosecond laser machining assisted with chemical etching are not clear, especially in a liquid environment. In this paper, monocrystalline silicon was ablated by femtosecond laser in air and deionized water respectively and then etched by alkaline potassium hydroxide (KOH). The reflectivity, absorptivity, and transmissivity of monocrystalline silicon were tested. Experimental results showed that inverted pyramid (IP) structure could be processed on a monocrystalline silicon wafer by ablating the surface with a high-power laser under the air environment and a low-power laser under the deionized water environment, followed by KOH etching. Meanwhile, the optical properties of the monocrystalline silicon with IP structure were effectively improved.

Synthesis, Crystal Structures, and Nonlinear Optical Properties of Chalcone Doped by Titanium Dioxide Nanoparticles for Solar Cell Application

In this work, we investigate the effects of titanium dioxide (TiO2) nanoparticle percentages on the optical and electrical properties of 3-(4-(dimethyl-amino)phenyl)-1-phenyl-(2E)-propen-1-one (DAAP). In order to achieve thin films, DAAP was dissolved in acetone and doped with different ratios of TiO2. The pure and composite mixtures were spin-coated onto a glass substrate. We investigated the influence of TiO2 on XRD patterns, absorption, energy band gaps, refractive indices, sheet resistance, resistivity, and Hall coefficients. We used the XRD technique to study the structure of DAAP pre- and post-doping with TiO2 nanoparticles. It was evident from the XRD patterns that the composite transformed from an amorphous to a polycrystalline nature and behaved similarly to titanium oxide crystals. The pure sample exhibited an absorption band of 409 nm. With the addition of TiO2, the whole absorption spectrum shifted to the blue region. For example, with a dopant percentage of 15%, the spectrum shifted to a wavelength of 368 nm. The energy band gap values increased with a dopant concentration from 2.65 eV of pure DAAP to 2.91 eV of maximum dopant percentage (15%). The refractive index decreased to its lowest value of 2.47 with the increase in TiO2 concentration. The impact of increasing TiO2 percentage highly improved electrical characteristics by reducing the sheet resistance and resistivity to 905 k(Ω/sq) and 230 k on the (Ω · cm), respectively. An optimized DAAP doped with 15% TiO2 has been used as an n-type layer on a p-type monocrystalline silicon wafer (Si (111)) to fabricate η = 0.23% efficient solar cells. On the other hand, the amplified spontaneous emission (ASE) of the DAAP and dopant mixture was excited by the third harmonic generation (λex = 355 nm). The pure DAAP exhibits an ASE peak at 535 nm. The intensity decreased rapidly with increased dopant concentration, whereas the full width at half-maximum (FWHM) increased slightly.

Rapid anisotropic chemical etching for quick formation of novel octagonal pyramids on silicon surface for photovoltaics

A novel octagonal micro pyramid structure was formed by etching a monocrystalline silicon wafer (100) by employing a wet chemical anisotropic etching process. The main objective is to reduce the silicon wafer's front surface reflectance, improve surface morphology, enhance wettability, and increase the coverage area of the octagonal pyramids on the surface of silicon wafers. The reaction time of the etching process was kept precise under strict observation and control. The experimental results demonstrate a significant reduction in silicon wafers' optical surface reflectance, achieving the lowest reflectance of 8.87%, along with improved surface morphology, periodicity, and coverage of more than 88%. While adding hydrofluoric acid together with magnetic stirring (mechanical agitation) at 300 rpm was advantageous in forming the octagonal silicon pyramid with a high etch rate of 0.41 um/min and significantly reducing the reaction time.

IMPROVEMENT OF THE PASSIVATION PROPERTIES OF SiO<sub>2</sub> FILMS, GROWN BY THE METHOD OF RAPID THERMAL ANNEALING, AFTER CHEMICAL RCA TREATMENT

As it is known, increasing the efficiency of silicon solar cells is one of the most important tasks in modern alternative energy industry. Optimization of the antireflection and passivation layer is the most economical way to increase efficiency. In this work, the effect of pretreatment on the passivation properties of silicon dioxide (SiO 2 ) films grown by rapid thermal processing (RTP) at annealing temperatures of 900 and 950°C in a dry oxygen atmosphere, was studied. The growth of thin films of SiO 2 on the surface of monocrystalline silicon wafers was carried out in the AS-ONE 150 rapid thermal annealing chamber (France). Measurements of the lifetime of minority charge carriers by the non-contact microwave method showed that the best passivation of the samples is achieved by applying a preliminary three-stage chemical cleaning (RCA) of the surface of the n-type silicon wafers. IR spectroscopy confirmed the formation of a SiO 2 layer by the presence of an intense maximum at 1071 cm -1 , which was attributed to stretching vibrations of the "tensioncompression" type. The results of calculations of the optical constants of the obtained SiO 2 films using the reflection spectra and the SCOUT software show the presence of a silicon dioxide whose refractive index and extinction coefficient are close to the reference.

The surface residual stress of monocrystalline silicon in ultrasonic vibration–assisted diamond wire sawing

Monocrystalline silicon wafer is the most important raw material in chip manufacturing; wire sawing is the most common processing method of monocrystalline silicon wafer. The residual stress generated by cutting affects the subsequent polishing costs directly, as well as the fracture strength and mechanical integrity of the monocrystalline silicon wafer, thus affecting the service performance. In this paper, the generation mechanism of residual stress was analyzed based on diamond wire sawing technology. Then, based on Drucker-Prager (D-P) plastic constitutive model, the magnitude and distribution of residual stress of monocrystalline silicon chip under different process parameters were simulated by ABAQUS simulation software. Finally, the experiment of ultrasonic vibration–assisted diamond wire saw cutting monocrystalline silicon was conducted, and the residual stress of monocrystalline silicon chips were detected by blind hole method. During the detection, the strain values before and after drilling in three directions of monocrystalline silicon chips were measured by strain gauge rosette, and then the residual stress values were determined according to the strain values and the residual stress calculation theory. The experimental results showed that residual compressive stress remains on the surface of silicon wafer in both conventional wire sawing and ultrasonic vibration–assisted wire sawing. The residual compressive stress increases with the increase of the axial speed of wire saw, decreases with the increase of the wire saw feed speed, and fluctuates with the increase of the workpiece rotation speed. The residual compressive stress on the surface of the silicon wafer by ultrasonic vibration–assisted wire sawing is larger than that by conventional wire sawing. The simulation and experimental results have the same trend, which verifies the validity of the finite element model in this paper and provides theoretical support for the subsequent processing of single crystal silicon.

Emitter formation with boron diffusion from PECVD deposited boron-doped silicon oxide for high-efficiency TOPCon solar cells

We present a systematic study of emitter formation with dopant diffusion from boron (B)-doped hydrogenated silicon oxide (a-SiOx:H) deposited on textured n-type monocrystalline silicon (n-c-Si) wafers using a 13.56 MHz plasma-enhanced chemical vapor deposition (PECVD) system. The B atoms in the a-SiOx:H are activated and diffused into the n-c-Si wafer during a high-temperature annealing to form a p/n junction for solar cell application. Afterward, the B-doped SiOx layer is removed by hydrofluoric acid selective etching to obtain a clean surface for the deposition of AlOx passivation and SiNx antireflection layers. With the optimization of the PECVD deposition and the following annealing/etching processes, the B diffused region with a sheet resistance of 60–100 Ω/sq and a junction depth of 1.2–1.5 μm is obtained. A champion implied open-circuit voltage (iVoc) of 705 mV and a single-side saturated recombination current density (J0,s) of 17.6 fA/cm2 are obtained from a double-sided B diffused sample after the passivation with an atomic-layer-deposition (ALD) AlOx. In addition, the contact resistivity (ρc) at the metal/emitter interface is lower than 5 mΩcm2, where the metal contact is a Ti/Pd/Ag tri-layer structure. All of the material properties meet the requirements of high-efficiency solar cell. With the optimized emitter in the front, we made a SiOx and heavily phosphorus-doped polycrystalline silicon carbide (n-poly-SiCx) stack on the rear surface to form tunnel oxide passivated contact (TOPCon) solar cells. The results show that the iVoc of semi-finished TOPCon solar cell before metallization is more than 725 mV. Finally, a TOPCon solar cell with an efficiency of 24.24% is obtained, which is comparable with the TOPCon solar cells with the industrial thermally diffused emitter.

A solid strategy to realize heteroface selective emitter and rear passivated silicon solar cells

AbstractPassivated emitter and rear cell (PERC) with laser‐doped selective emitter (SE) has become mainstream in the PV industry. In this work, we report a solid strategy to realize heteroface monocrystalline silicon (mono‐Si) wafers for PERC‐SE solar cells by employing alkaline polishing to form a polished surface for the rear side and well‐established metal‐catalyzed chemical etching to form a honeycomb texture for the front side in one wet process successively. The key to success lies in the fact that the two back‐to‐back wafers inserted into one slot in the cassette are tightly attached together in MCCE etching so that only the exposed surfaces are etched to form textures, while the rear polished surfaces are still retained to avoid wrap‐around etching. With the strategy, the mono‐Si PERC‐SE solar cells achieve an average efficiency of over 22.0%, no poorer than that of the reference system (traditional alkaline texturing and rear acidic polishing), and have good light trapping capability for oblique incident light. Moreover, the total Si removal in the novel process is only ~0.4 g, which is far less than that in the traditional process. More importantly, the strategy can also double the throughput of existing texturing processes and significantly reduce the amount of etching waste. Therefore, the work is expected to provide a promising way to mass produce efficient mono‐Si PERC‐SE solar cells with a superior rear surface, achieved without increasing the number of processing steps, and lower cost.

Optical-electrical characteristics of Al/Gd2O3/(CZ-pSi)/Al diodes under gamma ray irradiation

This article aimed to report the results on the properties of Gd2O3/(CZ-pSi) diodes under various gamma ray irradiation dose rates (3, 6, 12, 18, 24, 30, 36, 42, 50 Gy). n-type Gd2O3 films were deposited on a p-type Czochralski-grown monocrystalline silicon (CZ-pSi) wafers by pulsed laser deposition (PLD) technique with varying building laser energies (500, 600, 700, 800, 900 mJ) at room temperature and pressure (3.3 × 10−2 Pa). Amorphous structures were perceived for all films by XRD. Band gaps of the films were modified by controlling the amount of Gd2O3 on CZ-pSi wafers by laser power during deposition and determined to be between 5.30 and 5.75 eV. The Gd2O3/(CZ-pSi) films were irradiated by a Co-60 gamma-ray source system. The current and voltage (I-V) measurements, before and after irradiation (0–50 Gy), indicated that the current decreases toward zero with increasing doses. Capacitance and voltage (C-V) measurements at frequencies of 10–1000 kHz before and after irradiation showed a shift towards the right side of the pre-irradiation curves for each film. The shift was observed in both I-V and C-V curves with increasing radiation doses at 100 kHz as the average of the frequencies used. Contrary to the decrease in current curves, there was an upward increase in capacitance curves of all films with increasing radiation dose. The best build-in potentials of 0.1 V (800 mJ), 1.2 V (500 mJ) and 1.4 V (600 mJ) were obtained for the laser deposition powers of the Gd2O3/(CZ-pSi) diodes. These results are promising for diodes to be used in the radiation detection applications such as in neutron and alpha particles detectors.

Detection of Monocrystalline Silicon Wafer Defects Using Deep Transfer Learning

Defect detection is an important step in industrial production of monocrystalline silicon. Through the study of deep learning, this work proposes a framework for classifying monocrystalline silicon wafer defects using deep transfer learning (DTL). An existing pre-trained deep learning model was used as the starting point for building a new model. We studied the use of DTL and the potential adaptation of MobileNetV2 that was pre-trained using ImageNet for extracting monocrystalline silicon wafer defect features. This has led to speeding up the training process and to improving performance of the DTL-MobileNetV2 model in detecting and classifying six types of monocrystalline silicon wafer defects (crack, double contrast, hole, microcrack, saw-mark and stain). The process of training the DTL-MobileNetV2 model was optimized by relying on the dense block layer and global average pooling (GAP) method which had accelerated the convergence rate and improved generalization of the classification network. The monocrystalline silicon wafer defect classification technique relying on the DTL-MobileNetV2 model achieved the accuracy rate of 98.99% when evaluated against the testing set. This shows that DTL is an effective way of detecting different types of defects in monocrystalline silicon wafers, thus being suitable for minimizing misclassification and maximizing the overall production capacities.

Investigation and multi-objective optimization of monocrystalline silicon wafering using wire electro-discharge machining

Monocrystalline silicon wafers are widely used as the primary material for solar cell production in the photovoltaic industry, owing to their high efficiency and sleeker aesthetic. Wafering is the primary process towards wafer production. The existing wafering processes have limitations of cracking, chipping, and high kerf loss, arising the need for cost-efficient and precise methods to produce wafers. In the present experimental work, an attempt has been made to explore the potential of Wire Electro-discharge Machining (WEDM) for wafer production and to gain an understanding of the effects caused by pulse on time (Ton), pulse off time (Toff), peak current (Ip), wire tension (WT), and wire feed rate (WFR) during the wafering process to achieve the optimal parametric setting for attaining maximum wafering speed and minimum surface roughness. The work material used was P-type monocrystalline silicon. Wafers thickness of 250 μm was produced, avoiding edge chipping. The experimentation was planned according to the face-centered central composite design. The obtained results were statistically analyzed, and response surface methodology (RSM) was used to model the wafering speed and surface roughness. From the analysis of experimental results, it was noticed that at the higher level of Ton and Ip, a maximum wafering speed of 2.574 mm/min was attained. In contrast, the minimum surface roughness of 1.57 μm was achieved at the lower level of Ton and Ip. The most significant process variables that influence the wafering speed and surface roughness are the Ton, Toff, and Ip. Micrographs of the wafer surface reveal the presence of micro craters, but there was no evidence of micro-cracks. The multi-objective optimization of the responses was done using the desirability approach, and the optimized values of wafering speed and surface roughness attained were 0.989 mm/min and 1.57 μm, respectively.

Texture engineering of mono-crystalline silicon via alcohol-free alkali solution for efficient PERC solar cells

Control of texture structures is an effective method to reduce surface reflectivity and enhance the efficiency of solar cells. In this paper, pyramid structures are prepared on mono-crystalline silicon wafers by cyclodextrin as surfactant to slow down the etching rate in alcohol-free alkali solution. Compared with volatile alcohol surfactant (e.g. isopropanol, IPA), the cyclodextrin not only possesses a relative high boiling point (1534.4 ℃), but displays non-toxic and biodegradable properties. Furthermore, the surface morphology, average reflectivity, surface recombination of mono-crystalline silicon wafers were studied in detail. The results show that cyclodextrin can decrease the size and depth of pyramid structures, and thus a lower average reflectivity of 7.5% was obtained. In addition, ray tracing simulation was performed to calculate the photo-generated carrier concentration of PN junction with different sizes of pyramids, and the conclusion is that the carrier concentration of small pyramids is much higher than that of large pyramids. Finally, the average efficiency of large-area mono-crystalline silicon PERC solar cells fabricated by cyclodextrin surfactant was 22.69%, which was 0.43% absolutely higher than that of conventional IPA surfactant.

Optimization of corner compensations in wet etching of silicon for a MEMS Z-axis accelerometer

Fabrication of planar MEMS accelerometers using micromachining and wet etching of surface structures on monocrystalline silicon wafer substrates poses several problems. One such problem is the preferential undercut of convex corners in the structure during chemical etch of silicon wafers. Resultant structures after etching are no longer the same as the design structure, leading to degradation in the performance of the device. The preferential undercut arises due to ‘wet anisotropic etching’ wherein the etchant has different etch rates along different crystal planes of the substrate. One of the methods to minimise this preferential undercut is to use compensation extension structures in the planar geometry of the device. In this paper, an accelerometer structure using a square extension has been studied in detail and the resulting dimensions are experimentally validated through fabrication and tests. Design steps and selection of optimal dimensions of the square compensation geometry are discussed considering etch depth with minimal undercut using KOH etching solution. Several samples of structures with three different dimensions of square extensions were fabricated and resultant device geometry was studied to establish the optimal extension dimensions with minimal undercut for the desired depth of etch.

Characteristics of the formation and composition of AlxGa1-xN/AlN/por-Si/Si(111) heterostructures grown using a porous silicon buffer layer

In this work, we studied the efficiency of introducing nanoporous silicon as a buffer layer in the growth of AlxGa1–xN/AlN/Si(111) on a single-crystal silicon by molecular beam growth technology. We also considered its influence on the morphological characteristics and atomic composition of the surface layers of heterostructures. As determined by X-ray diffraction, microscopic, and X-ray photoelectron methods, the heterostructure grown on Si(111) n-type monocrystalline silicon wafer with nanoporous por-Si buffer layer has a more homogeneous epitaxial layer, and the surface morphology of the layer is also more homogeneous.