Modified Booth Multiplier Research Articles

Efficient transmission of FECG signal using MIMO – OFDM

The extraction of Fetal Electrocardiogram (FECG) during labor or prenatal phases of pregnancy holds significant importance for early prediction of heart abnormalities. The accuracy of the extracted FECG is crucial for effective diagnosis, but the presence of external noises, particularly from the Maternal ECG (MECG), poses a major challenge in obtaining precise information. To address this issue in biomedical data processing, the study employs Finite Impulse Response (FIR) filters using an array multiplier. One notable challenge encountered in this process is the interference caused by external noises, leading to higher delay and power dissipation. In response, a modified High-Performance Multiplier (HPM) based modified booth multiplier is thoroughly reviewed and validated. This modification aims to enhance overall performance and enable high-speed operations in filtering the FECG signals. The effectiveness of these modified multipliers is assessed using ECG signal information collected from the MIT-BIH Arrhythmia Database, comprising 120 samples. In addition to noise filtering, the study explores the validation of Multiple-Input Multiple-Output Orthogonal Frequency Division Multiplexing (MIMO-OFDM) transceivers. These transceivers play a crucial role in ensuring the effective transmission of the extracted FECG signals. The research reveals a significant reduction, up to 80.4%, in both area and power dissipation during simulations conducted in Xilinx ISE 9.1 and Cadence Virtuoso. This achievement highlights the potential for improved efficiency and reliability in the processing and transmission of FECG signals, paving the way for advancements in early detection of fetal heart abnormalities.

VLSI Design and Implementation of Multipliers for DSP Applications

A multiplier is a critical building block found in processors, embedded systems, VLSI applications, application specific integrated circuits, and most DSP applications. Speed, area, and power are the three primary thrust characteristics in VLSI design. Low power and high speed is the desirable characteristic in many applications that can extend the battery's life expectancy and increase the frequency of operation. The goal of this project is to design, implement and analyse the performance of array multipliers, booth multipliers, Wallace tree multipliers, and modified booth multipliers. In this work multipliers with different bit widths are implemented on Spartan 3E FPGA and their performances are analysed. Among these architectures Wallace tree multiplier provides higher speed of operation and consumes lesser power.

POSIT vs. Floating Point in Implementing IIR Notch Filter by Enhancing Radix-4 Modified Booth Multiplier

The increased demand for better accuracy and precision and wider data size has strained current the floating point system and motivated the development of the POSIT system. The POSIT system supports flexible formats and tapered precision and provides equivalent accuracy with fewer bits. This paper examines the POSIT and floating point systems, comparing the performance of 32-bit POSIT and 32-bit floating point systems using IIR notch filter implementation. Given that the bulk of the calculations in the filter are multiplication operations, an Enhanced Radix-4 Modified Booth Multiplier (ERMBM) is implemented to increase the calculation speed and efficiency. ERMBM enhances area, speed, power, and energy compared to the POSIT regular multiplier by 26.80%, 51.97%, 0.54%, and 52.22%, respectively, without affecting the accuracy. Moreover, the Taylor series technique is adopted to implement the division operation along with cosine arithmetic unit for POSIT numbers. After comparing POSIT with floating point, the accuracy of POSIT is 92.31%, which is better than floating point’s accuracy of 23.08%. Moreover, POSIT reduces area by 21.77% while increasing the delay. However, when the ERMBM is utilized instead of the POSIT regular multiplier in implementing the filter, POSIT outperforms floating point in all the performance metrics including area, speed, power, and energy by 35.68%, 20.66%, 31.49%, and 45.64%, respectively.

Design of Multipliers Using Various Methods

Multipliers are highly on demand as they are used in tremendous areas such as digital signal processing applications, image processing application , and in various Microprocessors such as ARM, NVIDIA, Intel, DSP Processors such as DM270,DM320 etc. Many researchers are urging to improve the performance of the multipliers by adopting various methods. Most of the existing papers includes the work on Array multipliers, Wallace tree multiplier, Dadda multiplier and Booth multipliers. And few recent papers include Vedic Mathematics that have implemented most commonly used Urdhva Sutra. In this paper, various methods are implemented to design a multiplier such as Booth multiplier, Modified Booth multiplier, Urdhva multiplier and Nikhilam multiplier. All the methods are used to design for 8bit signed numbers by coding very efficiently in Verilog. This paper focuses on the design of multipliers that are very simple in structure such that there is no circuit complexity. The design is simulated using Xilinx ISE or ModelSim SE.

Synthesizable Verilog Code Generator for Variable-Width Tree Multipliers

Tree multipliers are fast multipliers which are important for timing-critical applications. However, due to the irregular multiplier structure, the process of coding a tree multiplier is often very time-consuming. In addition, it is difficult to generalize the multiplier codes for variable-width inputs. In this paper, the authors used Python scripts to generate Verilog codes for tree multipliers automatically in a very short amount of time, by specifying only the required data width. The generated tree multiplier designs are synthesized and implemented using TSMC 180nm technology as well as Artix-7 FPGA. Through analysis, it is observed that modified Booth multiplier designed with Dadda tree reduction algorithm has up to 47% smaller area and up to 71% shorter delay compared to array multiplier. All multiplier designs are thoroughly simulated and functionally verified.

High-Speed Hybrid Multiplier Design Using a Hybrid Adder with FPGA Implementation

The major role of electronic devices is providing low power dissipation and high speed with compact area. The speed of electronic devices depends on arithmetic operations. Multiplication is the important arithmetic operation in many VLSI signal processing applications. Hence, a high-speed multiplier is needed to design any signal processing module. Many multipliers are surveyed in the literature. They are Array, Wallace tree, booth, Vedic and Compressor-based multiplier. The speed of these multipliers depends on partial product accumulation. The hybrid parallel adder-based multiplier is proposed to improve the speed of multiplication compared to the existing technique. In this technique the partial products of, two consecutive bits (multiplicands), are added simultaneously with the help of a hybrid adder (Hancarlson, Weinberger and Ling adder). The proposed architecture is synthesized and simulated using Xilinx ISE 12.1 with various FPGA boards. Synthesized report shows that the speed of proposed multiplier (Spartan 6 FPGA implementation) is improved when compared to an Array multiplier (22.14%), Wallace tree multiplier (20.41%), Multiplier using compressor (13.89%), Vedic Multiplier using CLA (13.03%), Vedic Multiplier using RCA (3.54%), Modified Booth multiplier (4.42%) and Vedic Multiplier using HCA with BEC (3.28%).

Simple and hardware‐efficient row‐based direct‐mapping estimators in fixed‐width modified Booth multipliers

SummaryThe great demand of high‐performance fixed‐width two's‐complement modified Booth multipliers (FWBM) arises because of the wide applications of approximate computing. In this paper, a row‐based direct‐mapping (RDM) method for designing error estimators in FWBM is proposed. The proposed closed form is derived from probability summation of each entire row to avoid the long setup time of exhaustive simulations. Consequently, a simple and systematic procedure by the Karnaugh map can be utilized to design low‐error and hardware‐efficient compensation circuits for various widths of FWBMs. By checking the leading column of the truncation part, the extendable design principle can be easily applied to different lengths and different columns inspected. We use Synopsys Design Compiler and TSMC 90 nm standard cell library to synthesize the register transfer language (RTL) design of our proposed estimators. In addition, the RDM is synthesized using the Xilinx Vivado tool with Xilinx Kintex‐7 XC7K325T‐2FFG900C FPGA. Results of software simulation, hardware synthesis, and implementation experiment validate the high accuracy, hardware saving, and power efficiency of the proposed RDM estimators.

뉴럴 프로세싱을 위한 Radix-4와 Factored Radix-8 기반 Modified Booth 곱셈기 설계 및 비교

뉴럴 프로세싱을 위한 Radix-4와 Factored Radix-8 기반 Modified Booth 곱셈기 설계 및 비교

Performance Analysis of High Speed and Area Efficient Finite Impulse Response Filters

This study represents the designing and implementation of a bandpass finite impulse response (FIR) filter of order 31 using windowing techniques. The frequency parameters used are of a typical GSM receiver,19 which is one of the applications of software-defined radio (SDR). To minimize filter area, various multiplication techniques like a canonical signed digit, Vedic multiplier, booth multiplier, and modified booth multiplier are used. Adders like ripple carry adder, carry save adder, carry look ahead adder, and Kogge-Stone adder are used to add the product from the multiplier unit. A comparison between three different windows has been made. The FIR is designed in MATLAB using a windowing technique. Then it is synthesized on Xilinx 14.7, Virtex 6 XC6VLX760, whose results are included in this paper.

FFT Implementation using Modified Booth Multiplier and CLA

In the field of digital signal and image processing the Fast Fourier Transform (FFT) is one of the rudimentary operations. Telecommunication, Automotive, Hearing devices, Voice recognition systems are some of the applications of Fast Fourier Transform. DFT is implemented using FFT which is a type of algorithm that computes DFT in a fast and efficient manner. This project concentrates on the development of the Fast Fourier Transform (FFT), based on Decimation In Time (DIT) domain, Radix2 algorithm, using VHDL as a design entity.The objective of this project is to establish an efficient design that computes FFT in a faster way. In this project FFT is implemented using modified booth multiplier and CLA and simulated on Xilinx ISE. K

Energy‐efficient VLSI implementation of multipliers with double LSB operands

Multiplication is an arithmetic operation that has a significant impact on the performance of various real-life applications, such as digital signal processing, image processing and computer vision. In this study, targeting to exploit the efficiency of alternative number representation formats, the authors propose an energy-efficient scheme for multiplying 2's-complement binary numbers with two least significant bits (LSBs). The double-LSB (DLSB) arithmetic delivers several benefits, such as the symmetric representation range, the number negation performed only by bitwise inversion, and the facilitation of the rounding process in the results of floating point architectures. The hardware overhead of the proposed circuit, when implemented at 45 nm, is negligible in comparison with the conventional Modified Booth multiplier for the ordinary 2's-complement numbers (3.1% area and 3.3% energy average overhead for different multiplier's bit-width). Moreover, the proposed DLSB multiplier outperforms the previous state-of-the-art implementation by providing 10.2% energy and 7.8% area average gains. Finally, they demonstrate how the DLSB multipliers can be effectively used as a building block for the implementation of larger multiplications, delivering area and energy savings.

Design of High-Speed Desensitized FIR Filter Employing Reduced Complexity SQRT Carry Select Adder

In this research, a highly efficient desensitized FIR filter is designed to enhance the performance of digital filtering operation. With regard to FIR filter design, Multiplication and Accumulation component (MAC) forms the core processing entity. Half-band filters employing Ripple Carry Adder (RCA) based MAC structures have a sizeable number of logical elements, leading to high delay and high power consumption. To minimize these issues, a modified Booth multiplier encompassing SQRT Carry Select Adder (CSLA) based MAC component is proposed for the desensitized filter with reduced coefficients and employing lesser number of logical elements forgiving optimum performance with respect to delay and power consumption. The suggested FIR filter is simulated and assessed using EDA simulation tools from Modelsim 6.3c and Xilinx ISE. The results obtained from the proposed Desensitized FIR filter employing the modified booth multiplier with reduced complexity based SQRT CSLA show encouraging signs with respect to 12.08% reduction in delay and 2.2% reduction in power consumption when compared with traditional RCA based digital FIR filter.

Low power and high performance FFT with different radices

<p>FFT is one of the most active blocks in digital signal processing and in various field of communication systems. FFT has received significant attention over the past years to increase its capability and versatility. This paper describes an extensive study on trade-off of different radices with different computational elements of butterfly such as adders and multipliers. Finding an efficient radix along with computational elements is the key point to find best suite i.e. high precision, low power and low area applications like radar, filtering, image compression etc. The work also considers the precision and the data format to represent constant value such as Q-point. The proposed FFT architectures not only uphold better solutions for low power and high-performance application systems, but also open up a new research lines. This paper demonstrates that radix-2^3 consumes 43% less LUTs and 17% less power consumption, 40% increase of frequency in radix-2^2 in comparison with radix- 2 algorithm for the combination of CSA with modified booth multiplier and the increment of frequency about 19%, 26% less LUTs consumption and 26% less power in Radix-2^2 when compared to radix-4 with various combination of adder and multiplier. In this work we have used Xilinx 14.7 XST for synthesis and the target device used is Spartan6 XC6SLX100. Simulation is carried out in Xilinx ISIM and also performed timing analysis and generated post-place and route.</p>

Design of modified booth based multiplier with carry pre-computation

Arithmetic unit is the most important component of modern embedded computer systems. Arithmetic unit generally includes floating point and fixed-point arithmetic operations and trigonometric functions. Multipliers units are the most important hardware structures in a complex arithmetic unit. With increase in chip frequency, the designer must be able to find the best set of trade-offs. The ability for faster computation is essential to achieve high performance in many DSP and Graphic processing algorithms and is why there is at least one dedicated Multiplier unit in all of the modern commercial DSP processors. Tremendous advances in VLSI technology over the past several years resulted in an increased need for high speed multipliers and compelled the designers to go for trade-offs among speed, power consumption and area. A novel modified booth multiplier design for high speed VLSI applications using pre-computation logic has been presented in this paper. The proposed architecture modeled using Verilog HDL, simulated using Cadence NCSIM and synthesized using Cadence RTL Compiler with 65nm TSMC library.The proposed multiplier architecture is compared with the existing multipliers and the results show significant improvement in speed and power dissipation.

Design and Implementation of FIR Filter usingLow Power and High-Speed Multiplier and Adders

The Finite Impulse Response (FIR) filter is robust and high stable architecture rather than Infinite Impulse Response (IIR) Filter for the speech and image processing applications. In this paper, a high speed and low power FIR filter is designed and implemented using Radix-4 modified Booth Multiplier and Carry Look Ahead (CLA) adder. The Booth multiplier reduces the accumulation computation time in the multiplication of filter inputs and coefficients. CLA is used to reduce the critical path delay of the normal Ripple carry adder, which is used for the addition for the FIR filter. The 8-tap direct form FIR filter is implemented using Booth multiplier and CLA, and it is simulated and synthesized. The delay and power corresponding to these blocks are computed and presented. The utilization summary with respect to target FPGA of the each and every block is also presented.

Design of quadruple precision multiplier architectures with SIMD single and double precision support

This paper proposes architectures for dual-mode and tri-mode dynamically configurable multiplier for quadruple precision arithmetic. The proposed dual-mode QPdDP multiplier architectures can either compute on a pair of quadruple precision (QP) operands or provide SIMD support for two-parallel (dual) sets of double precision (DP) operands. The proposed tri-mode QPdDPqSP multiplier architectures are aimed to include the four-parallel (quad) single precision (SP) along with dual-DP and a QP operand processing. For the underlying largest sub-component, the mantissa multiplier, two methods are analyzed to design the dual-mode/tri-mode architectures. One is based on the Karatsuba method, and in another a dual-mode/tri-mode Radix-4 Modified Booth (MB) multiplier is proposed. The proposed dual-mode/tri-mode MB multiplier requires few extra 2:1 MUXs as an overhead compared to a simple MB multiplier. To support dual-mode/tri-mode functioning other important sub-components of the FP multiplication are also re-designed for multi-mode support. The proposed architectures are synthesized using UMC 90 nm ASIC technology, and are compared against prior literature in terms of area, period, and a unified metric “Area (Gate Count) × Period (FO4) × Latency × Throughput (in cycles)”. The dual-mode/tri-mode FP architectures with MB mantissa multipliers shows better timings, however, those with Karatsuba mantissa multipliers acquires smaller area.

Fine-Tuning Accuracy Using Conditional Probability of the Bottom Sign-Bit in Fixed-Width Modified Booth Multiplier

In this paper, two methods for fine-tuning the accuracy of bias-estimation with conditional probability of the bottom signed bit (BSB) for fixed-width two’s complement modified Booth multiplier are proposed. We calculate the conditional probability between the BSB and partial product elements including other signed bits to estimate the expected value of truncation part. This makes fine-tuning of accuracy instead of column-wise coarse-tuning in fixed-width multipliers possible. We propose two methods based on the BSB to estimate and compensate the fixed-width multiplier for minimization of truncation error. Two proposed methods can improve the signal-to-noise (SNR) with a small area penalty in fixed-width multiplier. Statistics on the SNR were analyzed, and the hardware performance results validate the effectiveness of the proposed methods. In real-world implementation, compared with the discrete cosine transform (DCT) core using direct-truncated (D-T) multipliers, the DCT cores using the proposed BSB_AE and BSB_HC multipliers increase average peak signal-to-noise ratio (PSNR) by 27 and 31% with only a 6 and 7% area penalty, respectively.

Efficient Modified Booth Multiplier for Signal Processing Applications

The two’s complement approach plays a vital role in reducing Partial product Rows count in signed bit multiplier. In this paper proposed a multiplier which reduces the partial product rows by Modified Booth techniques with less delay. This high performance 2’s complement multiplier is used in embedded cores. This work was implemented in the Xilinx software and simulation results were obtained for the different applications. Applications such as FIR filter and Image processing requires high accuracy and smaller size multipliers. The image and filter interfacing is done with the help of MATLAB software.

Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division

Floating point division is a core arithmetic widely used in scientific and engineering applications. This paper proposed an architecture for double precision floating point division. This architecture is designed for dual-mode functionality, which can either compute on a pair of double precision operands or on two pairs of single precision operands in parallel. The architecture is based on the series expansion multiplicative methodology of mantissa computation. For this, a novel dual-mode Radix-4 Modified Booth multiplier is designed, which is used iteratively in the architecture of dual-mode mantissa computation. Other key components of floating point division flow (such as leading-one-detection, left/right dynamic shifters, rounding, etc.) are also re-designed for the dual-mode operation. The proposed dual-mode architecture is synthesized using UMC <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">90 nm</i> technology ASIC implementation. Two versions of proposed architecture are presented, one with single stage multiplier and another with two stage multiplier. Compared to a standalone double precision division architecture, the proposed dual-mode architecture requires 17% to 19% extra hardware resources, with 3% to 5% period overhead. In comparison to prior art on this, the proposed architecture out-performs them in terms of required area, time-period and throughput.

A Novel Architecture of FBMC Transmitter using Polyphase Filtering and its FPGA Implementation

Background/Objectives: In most of the Cognitive radio and frequency spectrum access we are using Filter Bank Multicarrier (FBMC) architecture; the Cognitive radio changes its parameters according to the environmental changes to operating the data in transmitting and receiving. This design makes use of FBMC to process according to parameter changes. Methods/Statistical Analysis: Here we design an efficient Architecture for FBMC Transmitter using Polyphase filter technique. The polyphase filter contains low power FIR Filters, Modified Booth multipliers, Carry save adders and it is flexible to fixed-point and floating point arithmetic. We are using Pipelined architecture to design an IFFT Module in the transmitter. Findings: The proposed FBMC Transmitter is better in terms of performance, complexity overhead compared to conventional methods. The FBMC Transmitter is designed and implemented on Artix 7 FPGA and compared with different FPGA’s and Results are verified on Chip Scope pro tool. Applications/Improvement: FBMC as a new concept in cognitive radio applications for dynamic access spectrum management purpose.