Modified Booth Multiplier Research Articles

Energy-Efficient Multiple-Precision Floating-Point Multiplier for Embedded Applications

Floating-point (FP) multipliers are the main energy consumers in many modern embedded digital signal processing (DSP) and multimedia systems. For lossy applications, minimizing the precision of FP multiplication operations under the acceptable accuracy loss is a well-known approach for reducing the energy consumption of FP multipliers. This paper proposes a multiple-precision FP multiplier to efficiently trade the energy consumption with the output quality. The proposed FP multiplier can perform low-precision multiplication that generates 8-, 14-, 20-, or 26-bit mantissa product through an iterative and truncated modified Booth multiplier. Energy saving for low-precision multiplication is achieved by partially suppressing the computation of mantissa multiplier. In addition, the proposed multiplier allows the bitwidth of mantissa in the multiplicand, multiplier, and output product to be dynamically changed when it performs different FP multiplication operations to further reduce energy consumption. Experimental results show that the proposed multiplier can achieve 59 %, 71 %, 73 %, and 82 % energy saving under 0.1 %, 1 %, 5 %, and 11 % accuracy loss, respectively, for the RGB-to-YUV & YUV-to-RGB conversion when compared to the conventional IEEE single-precision multiplier. In addition, the results also exhibit that the proposed multiplier can obtain more energy reduction than previous multiple-precision iterative FP multipliers.

High Speed 16×16-bit Low-Latency Pipelined Booth Multiplier

<b> </b><b> </b>This paper presents a high-speed 16×16-bit CMOS pipelined booth multiplier. Actually in an n-bit modified Booth multiplier, because of the last sign bit, n/2 +1 partial product rows are generated rather than n/2. The extra row not only increases the delay and power consumption of Wallace tree, but also it leads to irregularity and complexity of Wallace tree designing. In this multiplier the last sign bit is removed by using a simple high-speed approach. This causes 4% reduction in power consumption and 5.2% reduction in transistor count. Also by using new partial product generation and booth encoder circuits and a novel adder, speed of pipelined multipliers is improved. By these new architectures, final adder performs 25 bit addition in only two cycles with high speed (1.6 GHz). Due to lower number of cycles (5 clock cycles), delay of the overall circuit is only 3.1ns and besides power consumption is decreased so that at a data rate of 1 GHz and under the supply voltage of 3.3V, power consumption is 169mW. This multiplier is implemented in TSMC 0.35µm CMOS technology.

Modified Booth Multiplier with Carry Select Adder using 3-stage Pipelining Technique

This paper presents a high-speed and low area 16×16 bit Modified Booth Multiplier (MBM) by using Carry Select Adder (CSA) and 3-stage pipelining technique. These techniques improve the performance of MBM by reducing the delay time. Simulation results show that the delay is reduced by 56% and the number of SLICES and LUT’s are reduced by 4% respectively as compared to high speed MBM. The multiplier circuit is designed using VHDL and simulated using Xilinx ISE Simulator. The power metric of the MBM is evaluated using Cadence tools.

An Algorithm of Test Pattern Assignment of Circuit BIST Based on Gray Code

An algorithm is presented to reduce the power dissipation during test application for combinational circuits tested using built in self-test(BIST).The test sequence is generated by logic XOR operation between Group Gray code sequence and its canonical seeds to ensure that it is a single input change(SIC) sequence.According to the primary input weights of circuit,this algorithm properly assigns the Test Pattern Generator(TPG) outputs to the circuit based on the character of Gray code.The algorithm has been used for Modified Booth Multiplier(MBM).As compared to the conventional BIST scheme,the achieved reduction of power dissipation is from 35.6% to 43.7% depending on the size of the MBM.Testing results on the ISCAS'85 benchmark circuit show that the algorithm can achieve low power consumption and higher fault coverage while using less test patterns,and the power consumption is reduced by 59.3%~97.3% compared with LFSR at very small area overhead.Experimental results indicate that the proposed algorithm is very effective and applicable for low power BIST of embedded cores of systems on chip.

High-Accuracy Fixed-Width Modified Booth Multipliers for Lossy Applications

The fixed-width multiplier is attractive to many multimedia and digital signal processing systems which are desirable to maintain a fixed format and allow a little accuracy loss to output data. This paper presents the design of high-accuracy fixed-width modified Booth multipliers. To reduce the truncation error, we first slightly modify the partial product matrix of Booth multiplication and then derive an effective error compensation function that makes the error distribution be more symmetric to and centralized in the error equal to zero, leading the fixed-width modified Booth multiplier to very small mean and mean-square errors. In addition, a simple compensation circuit mainly composed of the simplified sorting network is also proposed. Compared to the previous circuits, the proposed error compensation circuit can achieve a tiny mean error and a significant reduction in mean-square error (e.g., at least 12.3% reduction for the 16-bit fixed-width multiplier) while maintaining the approximate hardware overhead. Furthermore, experimental results on two real-life applications also demonstrate that the proposed fixed-width multipliers can improve the average peak signal-to-noise ratio of output images by at least 2.0 dB and 1.1 dB, respectively.

Well-Structured Modified Booth Multiplier and Its Application to Reconfigurable MAC Design

This paper presents a well-structured modified Booth encoding (MBE) multiplier which is applied in the design of a reconfigurable multiply-accumulator (MAC) core. The multiplier adopts an improved Booth encoder and selector to achieve an extra-row-removal and uses a hybrid approach in the two's complementation circuit to reduce the area and improve the speed. The multiplier is used to form a 32-bit reconfigurable MAC core which can be flexibly configured to execute one 32×32, two 16×16 or four 8×8 signed multiply-accumulation. Experimentally, when implemented with a 130nm CMOS single-Vt standard cell library, the multiplier achieved a 15.8% area saving and 11.7% power saving over the classical design, and the reconfigurable MAC achieved a 4.2% area and a 7.4% power saving over the MAC design published so far if implemented with a mixed-Vt standard cell library.

Design of QR Decomposition Processor for GDFE

This paper presents a QR decomposition processor by exploiting Givens rotation for the GDFE (Generalized Decision Feedback Equalizer). A Givens rotation consists of phase extraction, sine/cosine generation and angle rotation parts. Combining two-stage method (coarse and fine stage) and the fixed-width modified-Booth multiplier, we design an efficient QR decomposition processor. By simulations, it is shown that the proposed QR decomposition processor can be a feasible solution for GDFE.

Efficient Dedicated Multiplication Blocks for 2´s Complement Radix-2m Array Multipliers

In this paper, we introduce new dedicated blocks for radix-2 m multiplication. These blocks are basic components of the structure of the 2´s complement radix-2 m array multiplier previously proposed in the literature. In the original array multiplier, the blocks that perform the radix-2 m multiplication were automatically synthesized from a truth table. The dedicated multiplication blocks we propose are themselves composed of a structure of less complex multiplication blocks and resort to efficient Carry Save adders (CSA). This new scheme can be naturally extended for different radices multiplication. We present results of area, delay and power consumption for 16, 32 and 64 bit array multipliers using the new dedicated modules. The results show that by using the new dedicated modules, the array multipliers are more efficient in terms of delay and power consumption when compared both against the original array structure and the Modified Booth multiplier.

Fixed-Width Group CSD Multiplier Design

This paper presents an error compensation method for fixed-width group canonic signed digit (GCSD) multipliers that receive a W-bit input and generate a W-bit product. To efficiently compensate for the truncation error, the encoded signals from the GCSD multiplier are used for the generation of the error compensation bias. By Synopsys simulations, it is shown that the proposed method leads to up to 84% reduction in power consumption and up to 78% reduction in area compared with the fixed-width modified Booth multipliers.

Multiplication Acceleration Through Twin Precision

We present the twin-precision technique for integer multipliers. The twin-precision technique can reduce the power dissipation by adapting a multiplier to the bitwidth of the operands being computed. The technique also enables an increased computational throughput, by allowing several narrow-width operations to be computed in parallel. We describe how to apply the twin-precision technique also to signed multiplier schemes, such as Baugh-Wooley and modified-Booth multipliers. It is shown that the twin-precision delay penalty is small (5%-10%) and that a significant reduction in power dissipation (40%-70%) can be achieved, when operating on narrow-width operands. In an application case study, we show that by extending the multiplier of a general-purpose processor with the twin-precision scheme, the execution time of a Fast Fourier Transform is reduced with 15% at a 14% reduction in datapath energy dissipation. All our evaluations are based on layout-extracted data from multipliers implemented in 130-nm and 65-nm commercial process technologies.

Modified Booth Multipliers With a Regular Partial Product Array

The conventional modified Booth encoding (MBE) generates an irregular partial product array because of the extra partial product bit at the least significant bit position of each partial product row. In this brief, a simple approach is proposed to generate a regular partial product array with fewer partial product rows and negligible overhead, thereby lowering the complexity of partial product reduction and reducing the area, delay, and power of MBE multipliers. The proposed approach can also be utilized to regularize the partial product array of posttruncated MBE multipliers. Implementation results demonstrate that the proposed MBE multipliers with a regular partial product array really achieve significant improvement in area, delay, and power consumption when compared with conventional MBE multipliers.

Testing Transition Delay Faults in Modified Booth Multipliers

This paper proposes a novel type of modified Booth multiplier and generates constant test pairs for single transition delay faults (TDFs) in multipliers of various sizes. All TDFs of the multipliers at cell and gate levels are C-testable with 10 and 27 patterns, respectively. These patterns can be generated by using a linear feedback shift register or a finite state machine, requiring a modest increase of 5% area for our 32 X 32 multiplier, for example. In addition, a method is proposed to generate 51% to 99% fewer patterns for the realistic sequential cell fault model (RS-CFM), when compared with a recent work. RS-CFM faults, which are claimed to be comprehensive in modeling sequential fault effects inside the cells, require all possible single-input-change patterns prepared for each cell. The proposed method generates 104 + 10 X Ny test pairs for RS-CFM in the Nx X N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">y</sub> modified Booth multiplier to achieve a similar fault coverage as the cited work.

전류모드 CMOS 4치 논리회로를 이용한 64×64-비트 변형된 Booth 곱셈기 설계

본 논문에서는 CMOS 다치 논리회로를 이용하여 <TEX>$64{\times}64$</TEX> 비트 Modified Booth 곱셈기를 설계하였다. 설계한 곱셈기는 Radix-4 알고리즘을 이용하여 전류모드 CMOS 4치 논리회로로 구현하였다. 이 곱셈기는 트랜지스터 수를 기존의 전압모드 2진 논리 곱셈기에 비해 64.4% 감소하였으며, 내부 구조를 규칙적으로 배열하여 확장성을 갖도록 설계하였다. 설계한 회로는 2.5V의 공급전압과 단위전류 <TEX>$5{\mu}A$</TEX>를 사용하여, <TEX>$0.25{\mu}m$</TEX> CMOS 기술을 이용하여 구현하였으며 HSPICE를 사용하여 검증하였다. 시뮬레이션 결과, 2진 논리 곱셈기는 <TEX>$7.5{\times}9.4mm^2$</TEX>의 점유면적에 9.8ns의 최대 전달지연시간과 45.2mW의 평균 전력소모 특성을 갖는 반면, 설계한 곱셈기는 <TEX>$5.2{\times}7.8mm^2$</TEX>의 점유면적에 11.9ns의 최대 전달지연시간과 49.7mW의 평균 전력소모 특성으로 점유면적이 42.5% 감소하였다. This paper proposes a <TEX>$64{\times}64$</TEX> Modified Booth multiplier using CMOS multi-valued logic circuits. The multiplier based on the radix-4 algorithm is designed with current mode CMOS quaternary logic circuits. Designed multiplier is reduced the transistor count by 64.4% compared with the voltage mode binary multiplier. The multiplier is designed with Samsung <TEX>$0.35{\mu}m$</TEX> standard CMOS process at a 3.3V supply voltage and unit current <TEX>$5{\mu}m$</TEX>. The validity and effectiveness are verified through the HSPICE simulation. The voltage mode binary multiplier is achieved the occupied area of <TEX>$7.5{\times}9.4mm^2$</TEX>, the maximum propagation delay time of 9.8ns and the average power consumption of 45.2mW. This multiplier is achieved the maximum propagation delay time of 11.9ns and the average power consumption of 49.7mW. The designed multiplier is reduced the occupied area by 42.5% compared with the voltage mode binary multiplier.

Low Power Small Area Modified Booth Multiplier Design for Predetermined Coefficients

In this paper, based on the variation of the modified Booth encoding method, an efficient modified Booth multiplier design method for predetermined coefficient groups is proposed. In the case of pulse-shaping filter design used in CDMA, it is shown that by the proposed method, area and power consumption can be reduced up to 44% and 48%, respectively, compared with the conventional designs. Also, it is shown that in the case of 128-point radix-24 FFT, the area and power consumption can be reduced by 18% and 36%, respectively.

A new array architecture for signed multiplication using Gray encoded radix- [formula omitted] operands

We present a new architecture for signed multiplication. The proposed architecture maintains the pure form of an array multiplier, exhibiting a much lower overhead than the Booth architecture. We propose a Hybrid encoding for the architectures, which is a compromise between the minimal input dependency presented by the Binary encoding and the low switching characteristic of the Gray encoding. The architecture uses radix- 2 m encoding, which leads to a reduction of the number of partial lines, enabling a significant improvement in performance and power consumption. Each group of m bits is encoded in Gray code, thus potentially enabling a further reduction of the switching activity both internally and at the inputs. The flexibility of our architecture allows for the easy construction of multipliers for different values of m , as opposed to the Booth multiplier for which implementations for m > 2 are complex. The results we present show that the proposed architecture with radix-4 compares favorably in performance and power with the Modified Booth multiplier. We have additionally implemented pipelined versions of these architectures. The results we present show that the proposed architecture with radix-4 also compares favorably in performance and power with the Modified Booth multiplier in the pipelined version.

A universal architecture for designing efficient modulo 2/sup n/+1 multipliers

This paper proposes a simple and universal architecture for designing efficient modified Booth multipliers modulo (2/sup n/+1). The proposed architecture is comprehensive, providing modulo (2/sup n/+1) multipliers with similar performance and cost both for the ordinary and for the diminished-1 number representations. The performance and the efficiency of the proposed multipliers are evaluated and compared with the earlier fastest modulo (2/sup n/+1) multipliers, based on a simple gate-count and gate-delay model and on experimental results obtained from CMOS implementations. These results show that the proposed approach leads on average to approximately 10% faster multipliers than the fastest known structures for the diminished-1 representation based on the modified Booth recoding. Moreover, they also show that the proposed architecture is the only one taking advantage of this recoding to obtain faster multipliers with a significant reduction in hardware. With the used figures of merit, the proposed diminished-1 multipliers are on average 10% and 25% more efficient than the known most efficient modulo (2/sup n/+1) multipliers for Booth recoded and nonrecoded multipliers, respectively.

Secondary radix recodings for higher radix multipliers

For progressively higher radices, the reduction in partial products obtained by the well-known modified Booth multiplier recoding is offset by the need to precompute a rapidly increasing store of odd multiples of the multiplicand as inputs to each partial product generator (PPG). We propose secondary radix multiplier recoding schemes reducing the number of odd multiples required in the store for very high radix recodings (e.g., radix 2/sup r/ for 5 /spl les/ r /spl les/ 16). The proposed recoding schemes allow reduction of the number of partial products in the implementation by factors between and beyond the reduction factors of 2, 3, and 4 that can be achieved by traditional Booth recodings to radices 4, 8, and 16, respectively. We develop the theory of these recodings and provide methodology for secondary radix selection. Finally, we summarize latency and cost evaluations of selected implementations indicating potential cost and performance/cost advantages for practical operand sizes.

Design of low-error fixed-width modified booth multiplier

This paper presents an error compensation method for a modified Booth fixed-width multiplier that receives a W-bit input and produces a W-bit product. To efficiently compensate for the quantization error, Booth encoder outputs (not multiplier coefficients) are used for the generation of error compensation bias. The truncated bits are divided into two groups depending upon their effects on the quantization error. Then, different error compensation methods are applied to each group. By simulations, it is shown that quantization error can be reduced up to 50% by the proposed error compensation method compared with the existing method with approximately the same hardware overhead in the bias generation circuit. It is also shown that the proposed method leads to up to 35% reduction in area and power consumption of a multiplier compared with the ideal multiplier.

Low Power Built‐In Self‐Test Schemes for Array and Booth Multipliers

Recent trends in IC technology have given rise to a new requirement, that of low power dissipation during testing, that Built‐In Self‐Test (BIST) structures must target along with the traditional requirements. To this end, by exploiting the inherent properties of Carry Save, Carry Propagate and modified Booth multipliers, in this paper we propose new power‐efficient BIST structures for them. The proposed BIST schemes are derived by: (a) properly assigning the Test Pattern Generator (TPG) outputs to the multiplier inputs, (b) modifying the TPG circuits and (c) reducing the test set length. Our results indicate that the total power dissipated during testing can be reduced from 29.3% to 54.9%, while the average power per test vector applied can be reduced from 5.8% to 36.5% and the peak power dissipation can be reduced from 15.5% to 50.2% depending on the implementation of the basic cells and the size of the multiplier. The test application time is also significantly reduced, while the introduced BIST schemes implementation area is small.

Modified Booth pipelined multiplication

A pipelined modified Booth multiplication is proposed for low power, high performance DSP application. The proposed multiplication is suitable for VLSI implementation. It has a better power-performance ratio than the traditional pipelined multiplier and modified Booth multiplier.