A new array architecture for signed multiplication using Gray encoded radix- [formula omitted] operands

Abstract

We present a new architecture for signed multiplication. The proposed architecture maintains the pure form of an array multiplier, exhibiting a much lower overhead than the Booth architecture. We propose a Hybrid encoding for the architectures, which is a compromise between the minimal input dependency presented by the Binary encoding and the low switching characteristic of the Gray encoding. The architecture uses radix- 2 m encoding, which leads to a reduction of the number of partial lines, enabling a significant improvement in performance and power consumption. Each group of m bits is encoded in Gray code, thus potentially enabling a further reduction of the switching activity both internally and at the inputs. The flexibility of our architecture allows for the easy construction of multipliers for different values of m , as opposed to the Booth multiplier for which implementations for m > 2 are complex. The results we present show that the proposed architecture with radix-4 compares favorably in performance and power with the Modified Booth multiplier. We have additionally implemented pipelined versions of these architectures. The results we present show that the proposed architecture with radix-4 also compares favorably in performance and power with the Modified Booth multiplier in the pipelined version.