A new pipelined array architecture for signed multiplication

Abstract

We present a new architecture for signed multiplication which maintains the pure form of an array multiplier, exhibiting a much lower overhead than the Booth architecture. This architecture is extended for radix-2/sup m/ encoding, which leads to a reduction of the number of partial lines, enabling a significant improvement in performance and power consumption. We have implemented a pipelined version of the radix-4 architecture in order to reduce both the critical path and useless signal transitions that are propagated through the array. The performance of our pipelined architecture is compared with the pipelined modified Booth. The results we present show that the proposed architecture with radix-4 compares favorably in performance and power with the modified Booth multiplier in the pipelined and non-pipelined approaches.