Modern IC Research Articles

INTERDISCIPLINARY ASPECTS OF INDUSTRY INNOVATIONS USE IN STUDY PROCESS AT UNIVERSITY

Abstract: The paper provides a brief analysis and exposes the need for more intensive use of ICT in combination with modern sources of renewable energy for efficient implementation of modern control and management technologies. Some interdisciplinary aspects of renewable energy and IC technologies use at universities are analyzed.
 The concept of interdisciplinary has been expanded not only in the field of interaction between different disciplines in the scientific field, in the field of education, but also in the field of application of modern energy and IC technologies to ensure the sustainabiliy of the university infrastructure.

RF-PSF: A CNN-Based Process Distinction Method Using Inadvertent RF Signatures

Stochastic variation of process parameters within a die and technology-limitation-driven variation from die-to-die give rise to unique distribution patterns for manufacturing process parameters. These patterns work as a process signature that is transferred from the device level to the system level through electrical circuits and can be used to make a distinction among the processes. In this work, we propose an in-situ manufacturing process technology distinction method‘, Radio Frequency Process Specific Functions (RF-PSF)’, that uses process-specific inherent properties of an IC manifested in the transmitted radio frequency signal. Among many desirable testing criteria, RF-PSF addresses the question of fabrication with the intended process technology. This information plays an important role in modern zero-trust architecture and IC clone detection, a counterfeiting method where the IC is manufactured using a different process. An RF transmitter with RF-DAC power amplifier for QPSK modulation has been designed and simulated in 14nm, 22nm, and 65nm processes for 5 process corners (TT, FF, FS, SF, and SS) in Cadence. The simulated data have been processed in MATLAB. A Multilayer Perceptron (MLP), trained with the constellation data, provides an average accuracy of ~90% for process distinction. Realizing that (i) a higher order modulation will have even more process information and (ii) we can harness the Convolutional Neural Network’s (CNN) improved capability on pattern recognition, we can feed image-like constellation plots to a CNN to get better and consistent performance. Using the baseband constellations for 64-QAM modulated data as images, we have achieved ~100% accuracy with commonly used, pretrained CNN models (ResNet18, ResNet50, and GoogleNet) through transfer learning. The separation among 5 process corners within a process, termed intra-process variation, is also analyzed. The effect of baseband sampling rate and ADC resolution, two practical limitations in RF systems, have been explored. An extensive study has been performed on the effect of a key design parameter at the RF circuit level i.e. W/L or aspect ratio, leading to design insights, proper CNN selection, and some control parameters. This work establishes RF-PSF as a zero-power, zero-area overhead, in-situ process distinction method.

Voltage Contrast within Electron Microscopy: From a Curious Effect to Debugging Modern ICs

Abstract A scanning electron microscope system measures voltage contrast on device-under-test surfaces. This article addresses a limited set of applications that rely on voltage contrast (VC) measurements in SEM systems, showing how VC measurements can probe electrical activity running at speeds as high as 2 GHz on modern active integrated circuits.

A memristor fingerprinting and characterisation methodology for hardware security

The modern IC supply chain encompasses a large number of steps and manufacturers. In many applications it is critically important that chips are of the right quality and are assured to have been obtained from the legitimate supply chain. To this end, it is necessary to be able to uniquely identify systems to aid in supply chain tracking and quality assurance. Many identifiers, however, can be cloned onto counterfeit devices and are therefore untrustworthy. This paper proposes a methodology for using post-CMOS memristor devices as a fingerprint to uniquely identify ICs. To achieve this, memristors’ unique and variable I–V characteristics are exploited to produce a fingerprint that can be generally applicable to a wide variety of different memristor technologies and identifiable over time, even where cell retention is non-ideal. In doing so it aims to minimise the hardware required on-chip both to minimise cost and maximise the auditability of the system. The methodology is applied to a text {TiO}_x memristor technology, and shown to be able to identify cells in a set.

A Universal Scaling Formulation of the Generalized Peck’s Equation for Corrosion Limited Lifetime in Self-Heated ICs

Since the early 1980s, the highly accelerated stress test in conjunction with conventional Temperature-Humidity-Bias testing has been the industry-standard method for interpreting relative humidity (RH) and temperature (T) dependent failure modes in non-hermetically packaged ICs, solar modules, and other electronic components. In recent years, however, testing requirements based on JEDEC standards and the corresponding lifetime extrapolation to end-use conditions using Peck’s equation have been criticized as overly conservative for modern self-heated logic/power ICs. In practice, the self-heated ICs correlate RH, and T in a way that is not explicitly accounted for by Peck’s equation. In this study, we investigate the IC lifetime due to electrochemical failures – Cu-Al bond wire corrosion – by considering the effects of ambient RH, T, duty cycle, and self-heating temperature rise using an integrated self-consistent finite element-based Multiphysics model and propose a generalized Peck’s equation for self-heated ICs. Our study reveals how the asymmetry between On and Off-state heating leads to dramatic suppression of the effective RH experienced by an integrated circuit and, most importantly, identifies that the corrosion of Cu-Al bond wire occurs in spikes during the on-off transition when both RH and T are high. The generalized Peck’s equation also predicts an elegant scaling relationship among the fundamental variables associated with a self-heated IC lifetime. The prediction is validated by experimental lifetime data from self-heated IC published in the literature. The experimental validation of the physics-informed generalized Peck’s equation suggests the possibility of more accurate (and optimistic) lifetime predictions of modern ICs and solar modules.

A current mode operational transconductance amplifier‐only half/full‐wave rectifier

AbstractThis letter introduces a novel half/full‐wave rectifier architecture that utilizes only an operational transconductance amplifier (OTA), eliminating the need for external passive components. The proposed circuit can accurately process input current signals with frequencies of up to 1 MHz, within an operating range of ±270 μA. The design exhibits excellent zero‐crossing performance, linearity, and simplicity, making it highly suitable for implementation in modern IC technologies. The impact of non‐idealities and parasitic effects on the circuit performance was thoroughly investigated; however, the absence of passive elements ensured that any parasitic effects remained negligible. The simulation results obtained using 0.18‐μm CMOS technology and a ±0.9 V supply voltage were consistent with theoretical predictions, validating the efficacy of the proposed design.

Concurrent Steiner Tree Selection for Global routing with EUVL Flare Reduction

The aggressive scaling down of the feature size in modern ICs has introduced major bottlenecks in printing layouts using a conventional 193nm immersion lithography system. As different mitigation techniques have reached their limitations, Next Generation Lithography (NGL) techniques have been gaining popularity. Extreme Ultra-violet Lithography (EUVL) system which uses light having 13.5nm wavelength is one of the popular NGL for printing features below 20nm. However, EUVL faces the problem of flare caused by irregular reflection from clear-field mask surfaces used. It leads to distortion of critical dimension (CD) during layout printing which in turn degrades the performance of the circuit. In this paper, we have formulated a delay-aware global routing problem in order to minimize flare without sacrificing the delay. Two different solvers, namely ILP and SAT-SMT, are employed and the results are compared. Experimental results show a significant reduction in flare without much compromise on delay.

POWER SNIFFER PERFORMANCE DEGRADATION AND WAYS TO SUPPRESS THE DEVIATION OF THE WORKING PARAMETERS DUE TO RANDOM TECHNOLOGICAL VARIATIONS

One of the most important challenges of modern ICs is power dissipation, particula-rly the static power dissipation. To be able to reduce static power consumption of an IC, it is separated into different power domains so that the supply power can be turned off for certain domain when not in use. Separate power domains lead to several peculiarities, one of them is the powering up and down the power supply. To represent the supply voltage state by another domain supply, circuits like power sniffers are used. With the evolution of the technologies, the role of random technological variations in the circuits becomes substantial. The paper presents ways to reduce the performance degradation caused by random variations in the 16nm technological process node. HSpice tool is used for circuit simulations. Target sigma representing random variations is 5. For every PVT 300 iterations with random variations are run. The results are presented by QQ plots and measurement table. By applying the proposed modifications performance degradation is reduced by around 40% (average for all measured parameters). By implementing the proposed circuit changes the area of the circuit is increasing by around 35%, no power consumption increase is observed.

Design of Proficient Two Operand Adder Using Hybrid Carry Select Adder with FPGA Implementation

In every modern ICs the adders are essential components. Adder’s performance has a substantial impact on the architecture of signal processing, controller, the module of filter, the module of data storage, etc., high-speed and area-efficient circuits are the most substantial parameters in every modern integrated circuit. Carry select adder operates at high speed, but it consumes more power due to the large area. The present approach discloses different VLSI hybrid carry select adder architectures. The hybrid technology-based Carry Select adder (CSELA) consists of two stages, namely the Hancarlson adder stage and Hybrid Stage is proposed. In this technique, all the stages (4 bits in each stage) are performed simultaneously to improve the speed and area further. The propagation delays of the proposed adder are the summation of two full adders, seven Multiplexers (4:1) and BEC(3 bit) for producing Cout. The proposed work indicates that the hybrid carry select adder operates at high a speed with a lesser area than the conventional adder. The proposed design is simulated and synthesized in Xilinx ISE 12.1 using Verilog HDL with a family of Vertex6 FPGA devices (Device No. XC6VLX75T, Package FF484, Speed -3). The synthesized report shows that the speed of the proposed adder is improved by 49.06%, 52.61%, 47.58%, 19.08%, 39.9%, 1.25%, 44.43%,19.08%, 44.07% and 71.59% compared to RCA, CBL-based CSELA, CLA, Weinberger BEC-based CSELA,D latched CSELA, Brent Kung CSELA, Brent Kung RCA-based CSELA, CSA Weinberger, Conventional CSELA and Ling CSELA, respectively.

PERIOD CHANGES OF MIRA VARIABLES IN THE M16-M17 REGION

We analyzed the light curves of 165 AGB variables, mostly Miras, in the sky area centered between M16 and M17 (l = 16, b = 0), using the OGLE GVS database in the IC band. Comparison with the published light curves, derived about 50 years earlier by P. Maffei using Kodak I-N photographic plates, allowed us to find no significant period changes in any star. Remarkably, a few stars of the sample appear to have substantially changed their average luminosity, the most striking case being KZ Ser. We provide a better identification for three stars: IX Ser, NSV 10522, and NSV 10326, all of them being Miras. We classify the light curves of 6 stars, discovered but not classified by Maffei, (GL Ser, NSV 10271, NSV 10326, NSV 10522, NSV 10677, and NSV 10772) five of them being new Miras, and confirm the R CrB nature of V391 Sct. The magnitude scale used by Maffei is compared to the modern IC one.

Space Charge Redistribution in Epoxy Mold Compounds of High-Voltage ICs at Dry and Wet Conditions: Theory and Experiment

Space charge profile plays an important role in defining the charge transport and breakdown field of an insulator. Non-destructive experimental techniques (e.g., PEA measurement) have recently been used to track in-situ the time-evolution of space charge profiles within complex insulators, such as epoxy mold compounds. Unfortunately, the published results are often inconsistent (both positive and negative charge build-up have been reported), and the discrepancy remains unexplained. In this paper, we (i) derive a physics-based compact analytical model of homocharge injection, (ii) explain the time-and voltage-dependent redistribution of homo- and heterocharge, (iii) investigate experimentally and explain theoretically the importance of moisture ingress regarding space charge redistribution, and finally, (iv) summarize strategies to suppress space-charge related instability in modern ICs encapsulated by epoxy mold compounds.

Combined therapy with inhaled glucocorticosteroids and long-acting β2-agonists in patients with bronchial asthma: the problem of choice

Bronchial asthma remains one of the most common chronic respiratory diseases. The apparent heterogeneity of BA underlies the concept of phenotype-specific or patient-centered therapy. However, in real clinical practice, BA continues to be regarded as a rather homogeneous pathological condition and its treatment in the vast majority of cases retains an empirical approach, the basis of which are inhaled glucocorticosteroids, usually in combination with long-acting beta2-agonists. Since this group of drugs is very representative, the physician is faced with the question of choosing the optimal drug. The basis of evidence-based medicine is a hierarchical classification, where systematic reviews, meta-analyses, and randomized clinical trials are considered the highest level of evidence. Because randomized clinical trials are conducted in carefully selected highly selected patient populations, they have little relevance to patients encountered in everyday clinical practice. In contrast, pragmatic randomized clinical trials assess the clinical efficacy of the investigational agent in a large, unselected population in which patients with comorbidities are included. In this context, the Salford Lung Study (SLS) is of particular interest. It was conducted before the registration of a new combination drug containing the modern ICS fluticasone furoate and the long-acting beta2-agonist vilanterol. The SLS results indicated not only that the use of fluticasone furoate with vilanterol provides better control of BA compared to continued "conventional therapy" (ICS ± LABAs) in symptomatic patients, but also leads to a consistent improvement in the surrogate parameters of quality of life.

(Invited) Cutting-Edge Epitaxial Processes for Sub 3 Nm Technology Nodes: Application to Nanosheet Stacks and Epitaxial Wrap-Around Contacts

The epitaxial growth of group IV semiconductor materials is one of the backbones of modern IC production flows. At present nodes it is used for the Source/Drain (S/D) engineering of both p- and n-MOS high performance transistors, allowing the deposition of SiGe:B and Si:P layers with active carrier concentrations ~ 1x1021 cm-3, ensuring low contact resistivities [1]. However, with reducing device dimensions, the growing importance of contact resistance in devices remains a major concern. A significantly lower parasitic S/D resistance could also be obtained thanks to the use of epitaxial and metal wrapped-around contacts (WAC) [2]. In addition, alternatives to Si channel materials (SiGe or Ge) and new device concepts such as 3D transistor stacking, complementary FET (CFET) and gate-all-around (GAA) nanosheet devices, all considered for the upcoming technological nodes of 3 nm and below [3], require process temperatures < 500ºC.To meet these temperature requirements, epitaxial processes based on the combination of high order Si and Ge precursors are explored together with low temperature Cl2 etching. The strength of this approach has already been demonstrated by the successful implementation of Ge/SiGe stacks and Ge S/D deposited at low temperature for the production of pMOS Ge GAA devices exhibiting excellent electrostatic control at sub-30 nm gate lengths [3].In this contribution, we use advanced low temperature epitaxial processes to enable cutting-edge applications. Complex and highly strained multi stacks are pseudomorphically grown with a limited thermal budget. The compositional contrast between the different parts of the stack, combined with very sharp interfaces, allows for the selective removal of sacrificial layers and the formation of active channels being totally isolated from parasitic channels in the substrate (Fig. 1(a)). In addition, highly B (Fig. 1 (b)) or B+Ga co-doped SiGe layers are grown at temperatures down to 400ºC with an active doping concentration exceeding 1x1021 cm-3. Epitaxial WAC structures are finally demonstrated Fig. 1 (c).[1] H. Wu et al., IEDM, 819 (2018)[2] S. Chew et al., 2017 IEEE Int. Interconnect Techn. Conf. (IITC), 1 (2017)[3] E. Capogreco, et al., Symposium on VLSI Technology , T94 (2019) Fig. 1. Example applications for advanced low temperature epitaxial growth processes. (a) HAADF-STEM cross-section image of a SiGe/Si multi stack used for the fabrication of nanosheet device with integrated bottom SiN/SiCO isolation; (b) B concentration profile measured by SIMS on a SiGe:B layer grown at low temperature, resulting in a carrier concentration above ~1x1021 cm-3. (c) Low temperature SiGe:B grown on Si fins demonstrating epitaxial WAC. Figure 1

Optimization for the quick-code methods for the synthesis of discrete signals – physical carriers of data in information-communication systems

The paper presents the theoretical foundations of synthesis and analysis of complex nonlinear discrete cryptographic signals, the basis for the synthesis of which are random (pseudo-random) processes, including algorithms for cryptographic transformation of information, as well as methods for optimizing the synthesis of these signals using decimation and discrete programming. namely, the method of branches and boundaries. In order to improve the performance of signal generation and processing, estimates of the effectiveness of the decimation procedure are proposed and presented. It is shown that the use of the studied signal systems will improve the efficiency of modern ICS (speed of data generation and processing devices, noise immunity, information security, secrecy, protection against input (imposition) of false messages, message falsification, data integrity, etc.).

Heatsinks as quasi-antennas and frog forming: frequency and feeding point effect

High-speed switching capabilities of modern ICs cause generating more heat, and it must be ejected via metallic heat-sinks behaving as an antenna at certain frequencies. Having different radiation patterns(RP) at different frequencies may cause a malfunction on nearby electronics placed on the other part of PCB. In this study, 50W equivalent heat-sink is investigated at 2-8 GHz in terms of feeding point. RP measurements and simulation results at four different feeding points are discussed, and it is observed that point of feeding is the pre-dominant factor of RP. As expected, the feeding of the heat-sinks from the center is to be preferred for lower frequencies, but it causes critical emission/interference problems at higher frequencies. As the frequency increases, it metamorphoses like a frog forming. While it behaves as an omnidirectional antenna having gain at 2GHz, RP turns to one that includes 6 beams with 30-degree beam-widths and gain.

An efficient NBTI-aware wake-up strategy: Concept, design, and manipulation

High leakage power consumption has become a serious problem in modern IC designs. By isolating a circuit block that is not in use from the power supply, power gating has become one of the most effective ways to reduce leakage power. During the circuit wake-up process, turning on sleep transistors simultaneously may induce an excessive surge current, which will threaten signal integrity. To avoid significant surge currents, sleep transistor wake-up sequences should be carefully designed. On the other hand, PMOS sleep transistors may suffer from the Negative-Bias Temperature Instability (NBTI) effect, where the wake-up time is increased after circuit aging. Conventional fixed wake-up sequence-based methods do not consider the NBTI effect, which may result in a longer or an unacceptable wake-up time after circuit aging. Therefore, in this paper, we propose a novel reconfigurable circuit structure that can reconfigure the wake-up sequence and a novel NBTI-aware wake-up strategy to reduce the wake-up time. Our strategy first finds a set of proper wake-up sequences under different aging circumstances and then dynamically reconfigures wake-up sequences at runtime based on an actual aging scenario (i.e. different months or years of aging). The experimental results show that compared with a traditional fixed wake-up sequence approach, our strategy can reduce up to 49.78% of the average wake-up time latency. In the meantime, according to our estimation, to implement the reconfigurable wake-up sequence structure, the parasitic area overhead is only about 0.27% with a larger benchmark.

From Cryptography to Logic Locking: A Survey on the Architecture Evolution of Secure Scan Chains

The availability of access to Integrated Circuits' scan chain is an inevitable requirement of modern ICs for testability/debugging purposes. However, leaving access to the scan chain OPEN resulted in numerous security threats on ICs. It raises challenging concerns particularly when the secret asset, like secret information, is placed within the chip, such as the keys of cryptographic algorithms, or similarly logic obfuscation key. So, to combat these threats, numerous secure scan chain architectures have been proposed in the literature to prevent any unauthorized access to the scan chain. They also keep the availability of the scan chain for testability/debugging. In this paper, we first show why a secure scan chain architecture is required when security primitives, like logic obfuscation, are in place. Then, we provide a holistic overview of all secure scan chain architectures starting from preliminary methods introduced when cryptography is in place and the adversary threat model is very limited. It is then followed by newer and more advanced methods introduced when logic obfuscation is in place and the adversary threat model is much stronger. Hence, we have more concentration on the architecture proposed more recently on logic obfuscation. We evaluate all secure scan chain architectures in terms of security and resiliency, testability/debugging time and complexity, and area/power/delay overhead.

Performance Comparison of Adder Topologies with Parallel Processing Adder Circuit

In today’s modern era IC architecture design adders are become obligatory block. The growth in digitalization scenario to produce compact design products parameters like power, delay and area should be minimized. In most of the complex design of digital circuits, adder is an elementary factor. If the performance of digital adders is enriched, it would lead to quickening the binary operations in involved in the complex circuits. The constraints in the operation delay of an adder are due to carry propagation in the circuit. The adder topologies involved in this work includes Carry Save Adder, Carry Select Adder, Ripple Carry Adder and Kogge Stone Adder

Comparative analysis of noise immunity of reception of nonlinear complex discrete signals with standard signals AFM-16 BPSK

The article shows that the solution to the problem of increasing the noise immunity (noise immunity and secrecy of functioning) of the ICS can be achieved using systems of nonlinear signals with improved ensemble, structural and correlation properties. Two classes of nonlinear complex discrete signals are considered: characteristic discrete signals (CDS) and cryptographic signals (CS). Methods for the synthesis of these signals are presented. The paper gives a statistical simulation model for studying the noise immunity of various classes of signals in the Gaussian channel. Using this model, estimates of the dependence of the error probability on the signal-to-noise ratio were obtained for various classes of signals, namely: CDS, KS and standard BPSK AFM-16 signals. It is shown that for the signal-to-noise ratio – 10 the error probability for the CDR is 4.6875e-06, for the CS is 3.515625e-06, and for the AFM-16 is 0.002025. Thus, the use of nonlinear complex discrete signals, in particular, CDS and KS, can significantly increase the noise immunity of signal reception in modern ICS. At the same time, taking into account the improved ensemble and structural properties of these nonlinear signals, it is possible to improve significantly the indicators of crypto- and imitation security of the systems functioning.

(Invited) Temperature Stable III-V/Si/Si3N4 Heterogeneous Integrated Laser

Silicon nitride (Si3N4) is a widely used complementary metal–oxide–semiconductor (CMOS) compatible material in modern IC industry and recent years have witnessed tremendous development of Si3N4 in photonics. The benefits of Si3N4 in photonics include low loss, low thermo optic coefficient and negligible nonlinear absorption at telecom wavelengths. Devices based on Si3N4 waveguides innovates in the field of nonlinear photonics, sensing, microwave photonics and so on. However, they are all dependent on the excellent passive properties of Si3N4. There are no successful demonstrations of fully integrated laser with Si3N4 yet.For an external cavity laser design, it is beneficial to have a low loss waveguide. A low loss waveguide platform can enable a long optical cavity which can greatly reduce the laser phase noise. Butt-coupled hybrid integrated lasers are extensively studied using Si3N4 cavity, but they are based on separate chips and are not scalable for large volume integration.Heterogeneous integration of III-V material and Si has achieved great success in the past years, offering the silicon photonics industry with low-cost, high-performance silicon photonic integrated circuits fully integrated with lasers. For the heterogeneous integration of III-V material with Si3N4, the biggest challenge is the large index mismatch. Typical III-V epi used for heterogeneous lasers is about 2 μm thick and extreme tapering cannot facilitate a high coupling efficiency between the III-V layer and Si3N4 layer.In this work, we used an intermediate Si layer to bridge the index mismatch between the III-V and Si3N4 layer. By using multilayer heterogeneous integration shown in Fig.1 (a), we enable a III-V/Si/Si3N4 structure to efficiently couple the mode between III-V/Si and Si/Si3N4. Based on this structure, we designed the III-V/Si/Si3N4 laser using an external Si3N4 spiral grating as the feedback cavity. This spiral grating provides the narrow-band optical feedback and determines the laser wavelength. The laser configuration is shown in Fig. 1(b).The laser performance is summarized in Fig. 1 (c)-(e). The lasing wavelength is at 1546 nm and the laser has over 58 dB side mode suppression ratio (SMSR). This shows the excellent mode selectivity from the 20 mm long Si3N4 spiral grating. We measured the frequency noise of the laser. With optimized loop mirror reflectivity, the laser fundamental linewidth is about 4 KHz. This linewidth can be further improved by lowering the Si3N4 waveguide loss. We anticipate the laser fundamental linewidth can be reduced to below 100 Hz using this design.Another advantage of integrating Si3N4 into the laser cavity is to have much higher temperature stability. By comparison, III-V/Si/Si3N4 laser wavelength shifts by only 0.47 nm for 45 oC change, while for a III-V/Si DBR laser this wavelength shift is 3.3 nm. This is over 7x difference and is a result of the low thermo-optic coefficient of Si3N4. When combined with Si3N4 based arrayed waveguide gratings, our laser can be potentially used in dense wavelength-division-multiplexing (DWDM) systems.The successful demonstration of this multilayer heterogeneous integration will enable a whole new class of devices that require low loss waveguides and are presently not integrated. This is a key step in fully exploiting the capabilities of wafer-bonding technologies. We anticipate this platform can take narrow-linewidth semiconductor laser performance to a new level. Figure 1