Threshold Voltage Model Research Articles

A physics‐based threshold voltage model for hetero‐dielectric dual material gate Schottky barrier MOSFET

AbstractThis paper presents the analytical model of threshold voltage for hetero‐dielectric dual material gate Schottky barrier (SB) metal oxide semiconductor field effect transistor (MOSFET). The threshold voltage model is derived on the basis of the surface potential model. The threshold voltage is extracted using transconductance change method. The two‐dimensional surface potential, electric field, and threshold voltage model for the hetero‐dielectric dual material gate SB‐MOSFET are developed using 2‐D Poisson's equation, which satisfies the boundary conditions. Moreover, the model precisely depict the impact of hetero‐gate dielectric and gate oxide thickness on the surface potential, and threshold voltage of the hetero‐dielectric dual material gate SB and compared with single material gate SB‐MOSFET. Finally, a good agreement between the model results and numerical simulated results is achieved.

3D analytical modeling of surface potential, threshold voltage, and subthreshold swing in dual-material-gate (DMG) SOI FinFETs

Here, we develop a 3D analytical model for potential in a lightly doped dual-material-gate FinFET in the subthreshold region. The model is based on the perimeter-weighted sum of a dual-material double-gate (DMDG) asymmetric MOSFET and a DMDG symmetric MOSFET. The potential model is used to determine the minimum surface potential needed to obtain the threshold voltage $$(V_{\mathrm{T}})$$(VT) and subthreshold swing (SS) by considering the source barrier changes in the leakiest channel path. The proposed model is capable of reducing the drain-induced barrier lowering (DIBL) as well as the hot carrier effects offered by this device. The impact of control gate ratio and work function difference between the two metal gates on $$V_{\mathrm{T}}$$VT and SS are also correctly established by the model. All model derivations are validated by comparing the results with technology computer-aided design (TCAD) simulation data.

Analytical Modeling of Threshold Voltage and Drain-Induced-Barrier- Lowering Variations Due to Gate Length Fluctuation in Nanometer MOSFETs

Analytical Modeling of Threshold Voltage and Drain-Induced-Barrier- Lowering Variations Due to Gate Length Fluctuation in Nanometer MOSFETs

Output characteristic and arc length control of pulsed gas metal arc welding process

A pulsed gas metal arc welding (P-GMAW) power source is produced with a stepped output characteristic. The steeped output characteristic control circuit is designed based on peak current-mode control and one cycle control methods An adaptive arc length control method is put forward and introduced based on a digital signal controller (DSC). Bead-on-plate experiments are carried out on mild steel to investigate the influences of output characteristics on the stability of P-GMAW process in an open-loop arc length control condition.Results show that stepped characteristic at background duration has the advantage of decreasing arc extinguishments and short-circuits phenomena, and the welding process is more stable without spatters than constant current or constant voltage characteristic. Welding with adaptive arc length control strategy, the dynamic behavior of arc working point and arc length is described, resulting in an identical arc length at the end of background time for each pulse period. One-drop-per-pulse transfer mode is obtained by carefully selecting pulse parameters with a droplet radius approximately equal to that of the electrode. Arc lengths are measured with different threshold voltages and background currents. The mathematical model of threshold voltage with respect to arc length and welding current is established through multiple linear regression analysis method. Welding with a step wire-feed speed and a step CTWD, the adaptive arc length control strategy shows strong disturbance resisting ability.

A Threshold Voltage Model of Silicon-Nanotube-Based Ultrathin Double Gate-All-Around (DGAA) MOSFETs Incorporating Quantum Confinement Effects

In this paper, a quantum-mechanical threshold voltage model for ultrathin double gate-all-around DGAA MOSFETs has been developed by solving three-dimensional (3-D) Poisson's and 2-D Schrodinger's equations in the channel region. The parabolic potential approximation is considered for Poisson's equation solution, whereas a hollow cylindrical potential well in the channel region is assumed to solve Schrodinger's equation. Simple equations for the wave function and energy quantization in the channel of DGAA MOSFET have been formulated. Discretized energy levels have been used for channel charge calculation in subthreshold regime of device operation. The calculated channel charge is compared with a threshold charge to formulate the threshold voltage model. The effects of the device parameters such as the channel thickness, oxide thickness, doping, etc. on threshold voltage and DIBL have been extensively studied. The proposed model results have been verified by comparing with the numerical simulation results obtained from the 3-D device simulator Visual TCAD of Cogenda Int.

Analytical Modeling of Surface Potential and Threshold Voltage for Junctionless Double Gate Vertical Slit Field Effect Transistor

Analytical Modeling of Surface Potential and Threshold Voltage for Junctionless Double Gate Vertical Slit Field Effect Transistor

A Surface Potential and Threshold Voltage Model Including Quantum Mechanical Effects for a Dual Material Double Gate Junctionless Field Effect Transistor (DMDG-JLFET)

A Surface Potential and Threshold Voltage Model Including Quantum Mechanical Effects for a Dual Material Double Gate Junctionless Field Effect Transistor (DMDG-JLFET)

A Threshold Voltage Model of Tri-Gate Junctionless Field-Effect Transistors Including Substrate Bias Effects

In this paper, the influence of substrate bias voltage and substrate-induced surface potential (SISP) on threshold voltage of tri-gate junctionless field-effect transistors (TG-JLFETs) has been investigated. For this purpose, a quasi-3-D threshold voltage model of TG-JLFETs is presented considering the effects of both back-bias voltage and a lightly doped substrate. To incorporate the effect of SISP on the threshold voltage, the boundary conditions at the silicon–buried oxide interface have been modified accounting for the potential difference between substrate surface and substrate bulk. Model results are compared with the simulation results obtained using 3-D visual TCAD device simulator from Cogenda.

A threshold voltage and drain current model for symmetric dual-gate amorphous InGaZnO thin film transistors

Based on the drift-diffusion theory, a simple threshold voltage and drain current model for symmetric dual-gate (DG) amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) is developed. In the subthreshold region, most of the free electrons are captured by trap states in the bandgap of a-IGZO, thus the ionized trap states are the main contributor to the diffusion component of device drain current. Whereas in the above-threshold region, most of the trap states are ionized, and free electrons increase dramatically with gate voltage, which in turn become the main source of the drift component of device drain current. Therefore, threshold voltage of DG a-IGZO TFTs is defined as the gate voltage where the diffusion component of drain current equals the drift one, which can be determined with physical parameters of a-IGZO. The developed threshold voltage model is proved to be consistent with trap-limited conduction mechanism prevailing in a-IGZO, with the effect of drain bias being also taken into account. The gate overdrive voltage-dependent mobility is well modeled by the derived threshold voltage, and comparisons of the obtained drain current with experiment data show good verification of our model.

Analytical modeling of subthreshold characteristics by considering quantum confinement effects in ultrathin dual-metal quadruple gate (DMQG) MOSFETs

In this work, analytical models of subthreshold characteristics for an ultrathin dual-metal quadruple gate MOSFET have been developed by considering the quantum confinement effects. The 2D Schrödinger’s equation has been solved analytically to obtain the threshold voltage and subthreshold current of ultrathin dual-metal quadruple gate MOSFET with minimum cross-section of 3nm×3nm. The inversion charge density at the threshold condition is obtained by considering minimum sub-band energy levels with a square potential well approximation for a two dimensional (width and height) carrier confinement. The subthreshold characteristics have been analyzed by varying different device parameters like channel cross-section, gate length ratio, gate metal work functions and gate oxide thickness. Further, the effect of 2D charge carrier confinement on drain induced barrier lowering (DIBL) has also been discussed using the threshold voltage model. The proposed models are validated against the numerical simulation results obtained from 3D ATLAS device simulator.

Modeling and control of threshold voltage based on pull-in characteristic for micro self-locked switch

Micro self-locked switches (MSS), where execution voltage corresponds to the output signal, are efficient and convenient platforms for sensor applications. The proper functioning of these sensing devices requires driving accurate displacement under execution voltage. In this work, we show how to control the actuating properties of MSSS. This switch comprises microstructures of various shapes with dimensions from 3.5 to 180µm, which are optimized to encode a desired manufacture deviation by means of mathematical model of threshold voltage. Compared with pull-in voltage, threshold voltage is more easy to control the pull-in instability point by theoretical analysis. With the help of advanced manufacture technology, switch is processed in accordance with the proposed control method. Then, experimental results show that it is better, which have been validated by corresponding experiments. In addition, they can be known from experiments that the manufacturing technology is advanced and feasible, and its high resilience and stably self-locked function can achieve instantaneously sensing.

Improved analytical model of surface potential with modified boundary conditions for double gate tunnel FETs

In this paper, an improved analytical model of the channel surface potential in the tunnel field effect transistors is established with modified boundary conditions considering the source and drain depletion widths, avoiding the deviation of the channel potential and the overestimate on the electric field. Based on the proposed surface potential model, the threshold voltage model is also developed with the transconductance change method. The influences of the channel and oxide structures on surface potential and threshold voltage are investigated. The good agreement is obtained by the comparison of the modeling results with the numerical simulation results, verifying the validation of the proposed model, and it also implied that this model will be helpful for the further investigation of TFETs.

Compact 2D threshold voltage modeling and performance analysis of ternary metal alloy work-function-engineered double-gate MOSFET

The present work aims to ameliorate the recently popular innovative gate engineering concept of continuously varying the mole fraction in a binary metal alloy gate electrode along the horizontal direction and realize a ternary metal alloy gate electrode. Based on this, a new ternary metal alloy (TMA) double-gate MOSFET has been proposed and a detailed two-dimensional analytical modeling has been presented to make an overall performance comparison of this proposed TMA double-gate MOSFET with that of its binary metal alloy gate counterpart in terms of surface potential, electric field, threshold voltage roll-off, drain-induced barrier lowering and current in order to establish the superiority of a ternary metal alloy gate electrode over its binary metal alloy equivalent. Analytical results have been compared with SILVACO ATLAS device simulator results to validate our present model.

A Novel Localized-Trapped-Charge-Induced Threshold Voltage Model for Double-Fin Multi-Channel FETs (DFMcFETs)

With the effects of localized trapped charges on the flat-band voltage, a novel localized-trapped-charge-induced threshold voltage model for the double-fin multi-channel FET (DFMcFET) is presented based on the quasi-3-D scaling equation and minimum bottom-central potential. It is shown that the deep trench of the DFMcFET is superior to the shallow one in respect of reducing the localized-trapped-charge-induced threshold voltage degradation (LTTVD). Besides, the low drain voltage ${V_{\mathrm{ ds}}}$ , the low trapped charge density ${N_{f}}$ , the small damaged zone near the drain side ${L_{s}}$ and the thin gate oxide ${t_{\mathrm{ ox}}}$ are required to resist LTTVD as the normalized damaged zone is increased. The LTTVD can be well controlled by the scaling theory. With the fixed damaged zone and trapped charge density, the allowable minimum channel length can be uniquely determined according to the criterion of scaling factor. In comparison to the conventional FinFET, DFMcFET not only provides more conducting channel, but also suffers less threshold voltage degradation caused by the short-channel effects irrespective of trapped charge polarity. With its computational efficiency and simple form, the model can be easily used for the circuit application for DFMcFET.

2-D Analytical Modeling of Surface Potential and Threshold Voltage for Vertical Super-Thin Body FET

In this paper, a 2-D analytical model for surface potential and threshold voltage of novel vertical super-thin body (VSTB) FET has been derived by solving 2-D Poisson equation. The analytical surface potential expression for gate-side surface and sidewall side surface has been modeled using parabolic surface potential approximation. The threshold voltage model for the VSTB FET has been derived by applying strong inversion criterion at the surface potential minimum value. The threshold voltage model for the VSTB FET has been analyzed by varying the body thickness, oxide thickness, and channel doping concentrations. The drain-induced barrier lowering and threshold voltage roll-off parameters are also extracted and analyzed for different body thicknesses. The models for surface potential and threshold voltage have been compared with the results obtained from the 2-D numerical device simulator and a very good agreement between the two has been observed.

Study on the influence of γ-ray total dose radiation effect on the electrical properties of the uniaxial strained Si nanometer NMOSFET

The carrier microscopic transport process of uniaxial strained Si n-channel metal-oxide semiconductor field-effect transistor (NMOSFET) has been analyzed under γ-ray radiation. The variation of electrical characteristics of the uniaxial strained Si nanometer NMOSFET has also been investigated under the total dose radiation. The Capacitor-Voltage (C-V) and Current-Voltage (I-V) characteristics are measured at room temperature before and after irradiation for each sample. The results indicate that the drift of threshold voltage, the degradation of carrier mobility and the increase in leakage current because of the total dose radiation effect. Moreover, a two-dimensional analytical model of threshold voltage (Vth) and carrier mobility model have been developed due to the total dose irradiation taken into consideration. Based on the model, numerical simulation has been carried out by MATLAB. The influence of the total dose, geometry and physics parameters on threshold voltage was simulated. Moreover, to evaluate the validity of the model, the simulation results were compared with experimental data, and good agreements were confirmed. Thus, the experiment results and proposed model provide good reference for research on irradiation reliability and application of strained integrated circuit of uniaxial strained Si nanometer n-channel metal-oxide semiconductor field-effect transistor.

Physics-Based Generalized Threshold Voltage Model of Multiple Material Gate Tunneling FET Structure

A generalized 2-D analytical model of gate threshold voltage for multiple material gate Tunneling FET (TFET) structures is derived. The model can also be used for calculating threshold voltage of a single metal gate TFET. Surface potential model of a triple material double gate TFET has been developed by applying Gauss's law in the device. From the potential model, physics-based model of gate threshold voltage has been derived by exploring the transition between linear to quasi-exponential dependence of drain current on applied gate bias. The model includes the effect of gate and drain bias, gate material workfunction, oxide thickness, silicon film thickness, gate dielectric, and other device parameters. The accuracy of the proposed model is verified by comparing the results predicted by the proposed model to the results of the numerical model developed in Silvaco, Atlas.

Improved Metal Oxide Semiconductor Field Effect Transistor models with wide temperature range including cryogenic temperature

The analytical Metal Oxide Semiconductor Field Effect Transistor (MOSFET) models with wide temperature range including cryogenic temperature have been presented in this paper. Based on the Berkeley Short-channel IGFET Model (BSIM) core, the mobility model, the threshold voltage model, the velocity saturation model and the parasitic resistance model have been updated and added to precisely describe the characteristics of MOSFETs at wide temperature range. The presented models have been verified by different MOSFETs and a capacitor charge-discharge circuit at regular and cryogenic temperatures. The measurement and simulation results have demonstrated the considerable accuracy and general applicability of the proposed models.

A 2D Potential Based Threshold Voltage Model Analysis and Comparison of Junctionless Symmetric Double Gate Vertical Slit Field Effect Transistor

ABSTRACT In the present paper, a two-dimensional (2D) potential-based analytical model of threshold voltage for junctionless symmetric double gate vertical slit field effect transistor (JL SDG VeSFET) is developed. The proposed model is based upon the solution of 2D Poisson's equation and is also extended to consider the effect of third dimension on threshold voltage of the device. The model includes the effect of various device parameters such as geometric gate length, dielectric thickness, substrate doping, and metal gate work function on threshold voltage, and is compared with conventional metal oxide semiconductor field effect transistor (MOSFET) device in order to show better performance of junctionless transistor and its application for future low power very large scale integration (VLSI) circuits. The analytical model is assessed with 2D TCAD Sentaurus simulation. The analytical model not only provides useful physical insight into the subthreshold behavior of the device, but also offers basic design guideline to better exploit its scaling potential for future nanoscale devices. It has been reported that the proposed model is in good agreement with simulative analysis with only a marginal deviation of about 3% for various device parameters.

2-D Analytical Modeling of the Electrical Characteristics of Dual-Material Double-Gate TFETs With a SiO2/HfO2 Stacked Gate-Oxide Structure

A physics-based 2-D analytical model for surface potential, electric field, drain current, subthreshold swing (SS) and threshold voltage of dual-material (DM) double-gate tunnel FETs (DG TFETs) with SiO2/HfO2 stacked gate-oxide structure has been developed in this paper. The parabolic-approximationtechnique, with suitable boundary conditions, has been used to solve Poisson’s equation in the channel region. Channel potential model is used to develop electric field expression. The drain current expression is extracted by analytically integrating the band-to-band tunneling generation rate over the channel thickness. Threshold voltage has been extracted by maximum transconductance method. The proposed model also demonstrates that the proper choice of work function for both the latterly contacting gate electrode (near the source and drain) materials which can give better results in terms of input-output characteristics, SS, and ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ than the conventional TFET devices. Although the proposed model has been primarily developed for Si-channel-based DM DG TFET devices, however, the model has also been shown to be applicable for other materials like SiGe (indirect bandgap) and InAs channel-based TFET structures. The results of the proposed model have been validated against the TCAD simulation results obtained by using SILVACO ATLAS device simulation software.