Transistor Model Research Articles

Accurate Evaluation of Commutations of 650 V GaN Power Switches Assisted by Electromagnetic Simulations in a 7 kW Dual Active Bridge Converter for Automotive Battery Charging Applications

The exploitation of high-voltage GaN power switches enables the development of power converters with superior characteristics with respect to components developed with heritage silicon-based technologies. One of the key advantages of GaN switches is their very fast commutation capability due to reduced parasitic capacitance and inductance with respect to silicon devices. The capability of an accurate evaluation of the switch commutations in the design phase is of crucial importance to maximize performance and avoid reliability or electromagnetic compatibility issues in the final converter. In this paper, an accurate evaluation of high-voltage GaN HEMT commutations is performed, exploiting detailed non-linear dynamic models of transistors and electromagnetic simulations of a PCB. A deep insight into the commutation waveforms in the intrinsic device (i.e., conductive drain current and intrinsic node voltages) is proposed to evaluate and explain the mechanisms of almost lossless turn-off and turn-on commutations in a 7 kW DAB converter. The influence on the performance of the PCB parasitics and the driver characteristics are accurately reproduced by simulations, suggesting important guidelines for the optimal design of power converters fully exploiting GaN HEMT’s potential. This detailed simulation/analysis approach for transistor commutation is typically adopted in Radio Frequency amplifier design but also becomes very valuable in power converter design when the very fast commutations of a GaN HEMT at a high switching frequency cannot be fully described and taken under control with conventional approaches used in power electronics design. The simulation results are confirmed by experimental data.

The Impact of Non‐Monolithic Semiconductor Capacitance on Organic Electrochemical Transistors Performance and Design

AbstractThe existing device models for organic electrochemical transistors (OECTs) fail to provide any device design guidelines for optimized performance parameters such as transconductance that are pivotal for the applications OECTs in sensing. Moreover, the current models are based on the questionable assumption of a homogenous organic semiconductor layer, and all predict a linear behavior of the resistance with the OECT channel length. Consequently, the experimentally observed nonlinear resistance behavior in OECTs has been overlooked thus far. Here, an OECT device model is developed that accurately describes the nonlinear behavior of the OECT channel resistance and offers the first guidelines for maximizing transconductance. The model is inherently nonlinear and the nonlinearity stem from the non‐monolithic capacitance of the organic semiconductor layer. Moreover, the model provides a consistent and reliable estimations for the contact resistance in OECTs. The success of the model in accurately describing and providing predictions of the OECT operation by relating the device's geometrical parameters with electrochemical parameters of the semiconductor layer paves the way toward unlocking OECT potentials in diverse applications, from biosensing to neuromorphic computing and flexible electronics.

Gaussian DOS Charge-Based DC Compact Modeling of High-Speed Organic Transistors

Gaussian DOS Charge-Based DC Compact Modeling of High-Speed Organic Transistors

Review and analysis on numerical simulation and compact modeling of InGaZno thin-film transistor for display SENSOR applications

Recent years have seen an increase in the use of Organic Thin Film Transistors (OTFTs), with applications ranging from flexible, low-cost displays to organic memory, RFID tag components, low-cost electronic appliances, and polymer circuits and sensors. Thin-film transistors (TFTs) have developed into a critical business on the grounds levels to their wide scope of utilizations in display; Radio-Frequency ID labels (RFID SENSOR), intelligent computation, and different areas. Reduced models are basic in the turn of events and execution of TFTs on the grounds that they overcome any barrier between the manufacture cycle and circuit plan. The motivation behind this exploration is to assemble a hypothetical structure for nanoscale TFT models made of polysilicon, indistinct silicon, natural, and In-Ga-Zn-O (IGZO) semiconductors. Extraordinary consideration is paid to surface-expected based smaller models of silicon-based TFTs. Surface-potential-based compact models and parameter extraction approaches were presented based on our knowledge of charge transport characteristics and TFT needs in organic and IGZO TFTs.

An efficient device model for ferroelectric thin-film transistors

Ferroelectric thin-film transistors (Fe-TFTs) have promising potential for flexible electronics, memory, and neuromorphic computing applications. Here, we report on a physics-based efficient device model for Fe-TFTs that effectively describes memory switching and device I–V characteristics. This model combines a stochastic multi-domain description of FE switching dynamics with a virtual source treatment of TFT device characteristics. It demonstrates that the memory window of Fe-TFTs depends on the amplitude and duration of the applied voltage pulses, thus suggesting quantitative means of programming and control. Additionally, we introduce a machine-learning-enabled method to automatically generate optimal voltage pulses for accurately programming multiple intermediate FE states, which is crucial for multi-bit memory and neuromorphic computing applications. To showcase the model’s applications, we simulate a 4×4 crossbar array circuit based on Fe-TFTs, highlighting its utility in performing multiply-accumulate computing operations. This small array can achieve a high speed of ∼1.28 tera operations per second (OPS) and a power efficiency of ∼0.43 W/PetaOPS. The model developed here is valuable for exploring the capabilities of Fe-TFTs in future flexible memory and computing technologies.

High-performance InGaZnO power transistors: Effect of device structural parameters

In this work, the effect of offset channel length (Loffset) and the dielectric layer thickness (d) on the InSnO/InGaZnO (ITO/IGZO) dual-active-layer (DAL) high-voltage thin-film transistors (HV-TFTs) is systematically investigated. The characteristics of the DAL HV-TFTs resemble that of GaN high electron mobility transistors, wherein the breakdown voltages (VBD) reach saturation at a certain Loffset, and the on-resistance (Ron) linearly increases with Loffset. The linear fitting of Ron vs Loffset indicates that d has a multifaceted impact on the performance of HV-TFTs. In addition to its theoretical role in transistor models, d also influences the channel doping concentration and sidewall deposition issues in practical devices. The DAL HV-TFT with a 30-nm Al2O3 gate dielectric achieves a remarkable VBD of 450 V, the highest figure of merit of 118.2 kW/cm2, and a positive threshold voltage of 3.65 V. Both experiments and simulations indicate that the breakdown occurs within the semiconductor channel, paving the way for further improvement of the performance.

Indirect Thermographic Measurement of the Temperature of a Transistor Die during Pulse Operation

This paper presents aspects related to the indirect thermographic measurement of a C2M0280120D transistor in pulse mode. The tested transistor was made on the basis of silicon carbide and is commonly used in many applications. During the research, the pulse frequency was varied from 1 kHz to 800 kHz. The transistor case temperature was measured using a Flir E50 thermographic camera and a Pt1000 sensor. The transistor die temperature was determined based on the voltage drop on the body diode and the known characteristics between the voltage drop on the diode and the temperature of the die. The research was carried out in accordance with the presented measuring standards and maintaining the described conditions. The differences between the transistor case temperature and the transistor die temperature were also determined based on simulation work performed in Solidworks 2020 SP05. For this purpose, a three-dimensional model of the C2M0280120D transistor was created and the materials used in this model were selected; the methodology for selecting the model parameters is discussed. The largest recorded difference between the case temperature and the junction temperature was 27.3 °C. The use of a thermographic camera allows the transistor’s temperature to be determined without the risk of electric shock. As a result, it will be possible to control the C2M0280120D transistor in such a way so as not to damage it and to optimally select its operating point.

Experimentally verified organic electrochemical transistor model

The Bernards–Malliaras model, published in 2007, is the primary reference for the operation of organic electrochemical transistors (OECTs). It assumes that, as in most transistors, the electronic transport is drift only. However, in other electrochemical devices, such as batteries, the charge neutrality is accompanied by diffusion-only transport. Using detailed 2D device simulations of the entire structure while accounting for ionic and electronic conduction, we show that high ion density (>1019 cm−3) results in Debye screening of the drain–source bias at the electrodes’ interface. Hence, unlike the drift-only current in standard FETs or low ion density OECTs, the current in high ion density OECTs is diffusion only. Also, we show that since in OECTs, the volumetric capacitor and the semiconductor are one, the threshold voltage has a different meaning than that in FETs, where the semiconductor and the gate-oxide capacitor are distinct entities. We use the above insights to derive a new model useful to experimentalists. Lastly, we fabricated PEDOT:PSS fiber-OECTs and used the results to verify the model.

Template models of silicon carbide JFETs and their practical applications in high-temperature analog chip design problems in LTspice environment

Modern achievements of leading microelectronic firms in the field of designing operational amplifiers (Op-Amp) and their functional units based on silicon carbide, designed for operation in the temperature range up to 300-600 °C, are analyzed. Numerical values of the parameters of existing high-temperature operational amplifiers, created for space missions of NASA Research Center named after Gallen, on the open-circuit voltage gain, the systematic component of the zero offset voltage, the frequency of single gain, the maximum rate of increase of the output voltage, the coefficient of attenuation of input in-phase signals and the coefficient of suppression of interference on the power supply rails, as well as information on the experimental characteristics of Op-Amps during long-term operation at high temperatures and exposure to radiation. To model circuits at temperatures up to 450 °C, template models of SiC transistors (TM) have been developed using the template modeling technique, in which constant model parameters are replaced by fractional-rational functions (Padé approximation), allowing to describe more accurately the physical processes in JFETs without violating the nature of their changes. For the freely distributable modeling environment LTspice the instruction for application of the TM is developed. Circuit solutions of high-temperature basic analog functional units realized on the basis of silicon carbide field-effect transistors are considered. The basic characteristics of SiC source repeaters, SiC differential stages and the simplest SiC operational amplifiers based on them at temperatures of 25 °C and 452 °C are investigated. The obtained results are recommended to be used in the design of high-temperature operational and instrumental amplifiers in space instrumentation, deep well drilling, automotive industry, nuclear reactors, etc.

On the Extraction of Accurate Non-Quasi-Static Transistor Models for E-Band Amplifier Design: Learning From the Past

On the Extraction of Accurate Non-Quasi-Static Transistor Models for <i>E</i>-Band Amplifier Design: Learning From the Past

(Invited) Analysis of Hysteresis in OTFTs Using a Physically-Based Compact Model

Organic TFTs (OTFs) have the potential to become essential devices for flexible, wearable and printed electronics. However, several issues related to their behavior still needs to be studied in detail and completely understood. One of these issues is hysteresis. In this abstract we analyze the hysteresis behavior in OTFT by applying a previously developed physically-based model to the direct (forward) and reverse (backward) dc sweeps of the transfer characteristics at different drain voltages. The identification of the model parameters which change provides more information about the hysteresis mechanism.The so-called UMEM (unified model and extraction method) model [1,2] developed for OTFT has been demonstrated to accurately reproduce the I-V characteristics for a wide range of geometries, bias and temperature conditions [3], as well as to extract physical values of most parameters. In this work we will show that it can reproduce the post-hysteresis I-V-characteristics of OTFT and that only a few parameters need to be changed.In the above threshold regime, where Variable Range Hopping dominates, the current is proportional to a field-effect mobility μFET= μ0(VGS-VT)γ/VAA γ , being VT the threshold voltage. The γ parameter depends on the DOS characteristic temperature T0 as = 2(T0/T-1).In the subthreshold regime diffusion dominates and the current is exponentially dependent on VGS:IDS=IDS0 exp (2.3(VGS-VT)/S) (1-exp(-VDS/Vth))where S is the subthreshold swing and Vth the thermal voltage.Aunified model of the drain current, valid and continuous from subthreshold to the above threshold regime, is finally obtained by means of a hyperbolic tangent function [1,2].In order to analyze the hysteresis behavior, this model was applied to both direct and reverse dc sweeps of the I-V characteristics of OTFT samples fabricated at CEA-Liten (Grenoble). Figs. 1 and 2 shows very good agreement from subthreshold toabove threshold. The parameter values extracted for the direct and reverse dc sweeps are shown in Table I. It is observed that the threshold voltage is shifted. The increase of γ indicates a higher degree of disorder in the reverse dc sweep characteristics. However, we can see that although IDS0 is higher, the extracted subthreshold swing value, S, does not change. The saturation parameter α is lower in the reverse sweep, but the rest of model parameters are not affected. Only γ and α show a variation with VDS, although rather small.[1] B. Iñiguez, et al., "New Compact Modeling Solutions for Organic and Amorphous Oxide TFTs," IEEE Journal of the Electron Devices Society, vol. 9, pp. 911-932, September 2021[2] C. H. Kim, et al., , “A Compact Model for Organic Field-Effect Transistors With Improved Output Asymptotic Behaviors,”IEEE Trans. on Electron Devices, vol. 60, no. 3, pp. 1136-1141, March 2013.[3] H. Cortés-Ordóñez, et al., “Parameter extraction and compact modeling of OTFT from 150 to 350K,”, Trans. on Electron Devices, vol. 67, no. 12, pp.5695-5692, Dec 2020.Acknowledgements:This work was funded by the Spanish Ministry of Science (PRX21/00726), and the EU EIC-PATHFINDER (BAYFLEX, no 101099555 Figure 1

GPU-Enabled Exascale Quantum Transport Modeling of Carbon Nanotube Devices

The work will describe our efforts to develop an exascale electrostatic-quantum transport framework, Quantum-eXstatic (https://github.com/AMReX-Microelectronics/eXstatic), currently supporting the modeling of carbon nanotube field-effect transistors (CNTFETs). The framework is capable of modeling realistic three-dimensional structures, efficiently, using CPU/GPU heterogeneous architectures of state-of-the-art supercomputers. It is built on top of the AMReX library, which is a GPU-enabled software library containing functionality for writing particle-mesh applications on structured grids. The Quantum-eXstatic framework comprises three major components: the electrostatic module, the quantum transport module, and the part that self-consistently couples the two modules. The electrostatic module using a finite-volume multigrid solver to compute the electrostatic potential induced by charges on the surface of carbon nanotubes, as well as by source, drain, and gate terminals, which can be modeled using an embedded boundary approach to allow for intricate shapes. The quantum transport module uses the Nonequilibrium Green's Function (NEGF) method to model induced charge. Currently, it supports coherent (ballistic) transport, mode-space approximation for subbands of nanotube, contacts modeled as semi-infinite leads, and Hamiltonian representation using the tight-binding approximation. Special features are being included for accurate modeling of long nanotubes, such as adaptive refinement of integration contours to resolve van Hove singularities in long channels. Particular attention is paid to overlap computations with communication to optimize GPU performance. The self-consistency between the two modules is achieved using Broyden's modified second algorithm, which is parallelized using CPUs and GPUs. Preliminary scaling studies show that the code exhibits ~77% weak-scaling efficiency on 512 NVIDIA A100 GPUs of Perlmutter supercomputer for modeling gate-all-around CNTFETs with a channel length of 13.5 microns at equilibrium conditions. This case involved computations of electrostatic potential in 14.5 billion computational cells and Green’s function computation for a Hamiltonian of size 131,072 x 131,072. For problems of this large size, the code takes about 5 min to reach self-consistency. Figure 1

Bionic modeling and neurocomputing of synaptic transistor based on egg white as gate dielectric

Bionic modeling and neurocomputing of synaptic transistor based on egg white as gate dielectric

DM-PA-CNTFET Biosensor for Breast Cancer Detection: Analytical Model

In this paper, an analytical model for a novel design dielectric modulated plasma-assisted carbon nanotube field-effect transistor (DM-PA-CNTFET) biosensor is proposed for breast cancer detection. This work is based on a PA-CNTFET in which CNT is used as a channel of FET, and various other device engineering techniques such as dual metal gate-all-around structure and dielectric stack of SiO2 and HfO2 have been used. A comparative analysis of DS-GAAE-CNTFET was performed using a silicon gate all-around FET (Silicon-GAA-FET)-based biosensor. Early detection of breast cancer is made possible by immobilizing MDA-MB-231 and HS578t into the dual-sided nanocavity, which alters the electrical properties of the proposed CNTFET-based biosensor. The DS-GAAE-CNTFET sensor demonstrates a drain ON current sensitivity of 236.9 nA and a threshold voltage sensitivity of 285.58 mV for HS578t cancer cells. Malignant MDA-MB-231 breast cells exhibit a higher drain ON current sensitivity of 343.35 nA and a corresponding threshold voltage sensitivity of 293.23 mV. The exceptional sensitivity and structural resilience of the DS-GAAE-CNTFET biosensor establish it as a promising candidate for early breast cancer detection.

A parameter extraction method for InP HBT small‐signal model considering emitter–collector laminated capacitance effect

AbstractThe extraction of small‐signal parameters is of great importance for the modeling of InP heterojunction bipolar transistors (HBTs). This letter proposes an improved small‐signal parameter extraction method that considers both the emitter–collector capacitance effect and the current crowding effect. The corresponding parameter extraction procedure based on closed‐form equations is outlined. Furthermore, the model parameter extraction method is validated using two different‐sized InP HBT devices with multibias S‐parameters. The results demonstrate that the established small‐signal model exhibits greater than 90% accuracy across the frequency range of 1–110 GHz. In particular, in the high‐frequency band (above 50 GHz), the proposed model exhibits an improvement in accuracy of 7.4% after considering the emitter–collector capacitance and current crowding effects. This method can contribute to accurate modeling of the noise and large‐signal performance of InP HBT.

Advances in CMOS Image Sensors and Transistors Leveraging Stochastic Nanomagnets: A Comprehensive Review

Accurate modeling and assessment of complex Complementary Metal-Oxide Semiconductor (CMOS) imaging sensors and transistors, in conjunction with randomized nanomagnets for distributed computation in radiated environments, are crucial for the development of robust electronic systems. The effectiveness and resilience of these intricate parts to radiation exposure is the subject of this study, which is becoming more and more important in applications including space missions, power plants, and high-altitude flying. To take into account the interaction between CMOS technology and the unpredictable behavior of nanomagnets, a comprehensive durability modeling technique is required. The methodology that has been suggested evaluates the susceptibility of image detectors and transistors to malfunctions caused by radiation, such as dislocation damage, single-event upsets (SEUs), and impacts of total ionizing dose (TID). The impact of radiation on the power characteristics and operational dependability of these components is investigated using state-of-the-art modeling tools and experimental data. The findings suggest that random nanomagnets can improve distributed computing devices' resistance to radiation-induced failures. Through the provision of insights into reliability challenges and solutions for enhanced CMOS image sensors and transistors, this work advances the field of radiation-tolerant technologies. Future electronic device developers will find the suggested reliability modeling and evaluation methodology to be a useful resource for creating reliable devices that can resist harsh radioactive environments. Keywords— Reliability Modeling; CMOS Image Sensors; Radiation Environment; Advanced Technology Node; Transistor Structures; Stochastic Nanomagnets; Heterogeneous Computing; Probabilistic Inference

Design of a compact MOSFET model suitable for geometric programming

ABSTRACT The design of analog integrated circuits is a demanding task that involves many constraints and objectives. Also, the transistor models employed must consider high-order physics effects to achieve accurate solutions. Geometric Programming (GP) allows finding the global minimum in optimisation problems, but requires design equations to be in monomial or posynomial form. This work proposes a simplified model inspired on the Advanced Compact MOSFET model tailored to be used in GP problems. The proposed model considers short-channel effects and it is valid in the saturation region with all inversion levels. The equations are presented, first showing the transistor current-voltage characteristic and then the associated capacitances. The validity of the equations is proven by their capacity to fit to the simulated data, achieving a mean error of 0.4% for the main NMOS characteristic. After that, the optimal design of two basic amplifier stages is performed to demonstrate the model usability with GP. The predicted voltage gain and bandwidth of the designed amplifiers are compared with simulations, presenting mean errors of 24.7% and 31.7%, respectively. These errors are low when viewed from a logarithmic perspective and considering the wide design space covered. As GP optimisation guarantees the global minimum location and does not require the usage of a circuit simulator in the loop, the proposed GP-friendly compact model can enable fast and accurate optimisation of analog integrated circuits.

On a Mott formalism for modeling oxide thin-film transistors

We report on a device model for thin-film transistors (TFTs) in the framework of Mott's trap-and-release transport theory for disordered semiconductors. The model features a so-called Mott function that is demonstrated to be powerful for analytically deriving the terminal characteristics and other critical parameters of TFTs, including threshold voltage, subthreshold swing, and field-effect mobility. The model is validated by way of application to an amorphous InGaZnO (IGZO)-based TFT, for which good agreement between the analytical and experimental data are obtained. This study offers a simple yet powerful formalism for effective parameter characterization and extraction for oxide and other related TFTs, including those from the organic materials family.

Spin Gapless Quantum Materials and Devices.

Quantum materials, with nontrivial quantum phenomena and mechanisms, promise efficient quantum technologies with enhanced functionalities. Quantum technology is held back because a gap between fundamental science and its implementation is not fully understood yet. In order to capitalize the quantum advantage, a new perspective is required to figureout and close this gap. In this review, spin gapless quantum materials, featured by fully spin-polarized bands and the electron/hole transport, are discussed from the perspective of fundamental understanding and device applications. Spin gapless quantum materials can be simulated by minimal two-band models and could help to understand band structure engineering in various topological quantum materials discovered so far. It is explicitly highlighted that various types of spin gapless band dispersion are fundamental ingredients to understand quantum anomalous Hall effect. Based on conventional transport in the bulk and topological transport on the boundaries, various spintronic device aspects of spin gapless quantum materials as well as their advantages in different models for topological field effect transistors arereviewed.

An improved small signal model of a mos transistor in millimeter wave band considering longitudinal distributed effects

An improved small signal model of a mos transistor in millimeter wave band considering longitudinal distributed effects